Type Definition cc3220sf::gspi::modulctrl::R

type R = R<u32, MODULCTRL>;

Reader of register MODULCTRL

Implementations

impl R

pub fn initdly(&self) -> INITDLY_R

Bits 4:6 - Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled. This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period. 0x0 No delay for first spi transfer. 0x1 The controller wait 4 spi bus clock 0x2 The controller wait 8 spi bus clock 0x3 The controller wait 16 spi bus clock 0x4 The controller wait 32 spi bus clock