Type Definition cc3220sf::gspi::ch1ctrl::R

type R = R<u32, CH1CTRL>;

Reader of register CH1CTRL

Implementations

impl R

pub fn extclk(&self) -> EXTCLK_R

Bits 8:15 - Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the max value reached is 4096 clock divider ratio. 0x00 Clock ratio is CLKD + 1 0x01 Clock ratio is CLKD + 1 + 16 0xFF Clock ratio is CLKD + 1 + 4080