[−][src]Type Definition cc3220sf::gspi::ch0ctrl::W
type W = W<u32, CH0CTRL>;
Writer for register CH0CTRL
Implementations
impl W
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pub fn extclk(&mut self) -> EXTCLK_W
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Bits 8:15 - Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the max value reached is 4096 clock divider ratio. 0x00 Clock ratio is CLKD + 1 0x01 Clock ratio is CLKD + 1 + 16 0xFF Clock ratio is CLKD + 1 + 4080