Module cc3220sf::aes

AES

Modules

auth_length	AAD data length. The authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM) Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any value up to (2^32 - 1) bytes can be used. Once processing with this context is started@@ this length decrements to zero. A write to this register triggers the engine to start using this context for GCM and CCM. For XTS this register is optionally used to load j. Loading of j is only required if j != 0. j is a 28-bit value and must be written to bits [31-4] of this register. j represents the sequential number of the 128-bit block inside the data unit. For the first block in a unit@@ this value is zero. It is not required to provide a j for each new data block within a unit. Note that it is possible to start with a j unequal to zero; refer to Table 4 for more details. For a Host read operation@@ these registers return all-zeroes.
c_length_0	Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started@@ this length decrements to zero. Data lengths up to (2^61 1) bytes are allowed. For GCM@@ any value up to 2^36 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 2@@ resulting in a maximum number of bytes of 2^36 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes@@ this length does not include the authentication only data; the authentication length is specified in the AES_AUTH_LENGTH register below. All modes must have a length > 0. For the combined modes@@ it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine. For a Host read operation@@ these registers return all-zeroes.
c_length_1	Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started@@ this length decrements to zero. Data lengths up to (2^61 1) bytes are allowed. For GCM@@ any value up to 2^36 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 2@@ resulting in a maximum number of bytes of 2^36 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes@@ this length does not include the authentication only data; the authentication length is specified in the AES_AUTH_LENGTH register below. All modes must have a length > 0. For the combined modes@@ it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine. For a Host read operation@@ these registers return all-zeroes.
ctrl	register determines the mode of operation of the AES Engine
data_in_0	Data register to read and write plaintext/ciphertext (MSW)
data_in_1	Data register to read and write plaintext/ciphertext
data_in_2	Data register to read and write plaintext/ciphertext
data_in_3	Data register to read and write plaintext/ciphertext (LSW)
irqenable	This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_x output. All interrupts need to be enabled explicitly by writing this register. ****************************************************************************
irqstatus	This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted
iv_in_0	Initialization Vector input (LSW)
iv_in_1	Initialization vector input
iv_in_2	Initialization vector input
iv_in_3	Initialization Vector input (MSW)
key1_0	Key (LSW for 128-bit key)
key1_1	Key
key1_2	Key
key1_3	Key (MSW for 128-bit key)
key1_4	Key (LSW for 192-bit key)
key1_5	Key (MSW for 192-bit key)
key1_6	Key (LSW for 256-bit key)
key1_7	Key (MSW for 256-bit key)
key2_0	XTS / CCM / CBC-MAC second key (LSW) / Hash Key input (LSW)
key2_1	XTS / CCM / CBC-MAC second key / Hash Key input
key2_2	XTS / CCM / CBC-MAC second key / Hash Key input
key2_3	XTS second key (MSW for 128-bit key) + CCM/CBC-MAC second key (MSW) / Hash Key input (MSW)
key2_4	XTS / CCM second key / CBC-MAC third key (LSW)
key2_5	XTS second key (MSW for 192-bit key) / CBC-MAC third key
key2_6	XTS second key / CBC-MAC third key
key2_7	XTS second key (MSW for 256-bit key) / CBC-MAC third key (MSW)
revision	Register AES_REVISION
sysconfig	Register AES_SYSCONFIG.This register configures the DMA signals and controls the IDLE and reset logic
sysstatus	SYSSTATUS
tag_out_0	TAG_OUT_0
tag_out_1	TAG_OUT_1
tag_out_2	TAG_OUT_2
tag_out_3	TAG_OUT_3

Structs

RegisterBlock

Register block

Type Definitions

AUTH_LENGTH	AAD data length. The authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM) Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any value up to (2^32 - 1) bytes can be used. Once processing with this context is started@@ this length decrements to zero. A write to this register triggers the engine to start using this context for GCM and CCM. For XTS this register is optionally used to load j. Loading of j is only required if j != 0. j is a 28-bit value and must be written to bits [31-4] of this register. j represents the sequential number of the 128-bit block inside the data unit. For the first block in a unit@@ this value is zero. It is not required to provide a j for each new data block within a unit. Note that it is possible to start with a j unequal to zero; refer to Table 4 for more details. For a Host read operation@@ these registers return all-zeroes.
CTRL	register determines the mode of operation of the AES Engine
C_LENGTH_0	Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started@@ this length decrements to zero. Data lengths up to (2^61 1) bytes are allowed. For GCM@@ any value up to 2^36 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 2@@ resulting in a maximum number of bytes of 2^36 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes@@ this length does not include the authentication only data; the authentication length is specified in the AES_AUTH_LENGTH register below. All modes must have a length > 0. For the combined modes@@ it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine. For a Host read operation@@ these registers return all-zeroes.
C_LENGTH_1	Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started@@ this length decrements to zero. Data lengths up to (2^61 1) bytes are allowed. For GCM@@ any value up to 2^36 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 2@@ resulting in a maximum number of bytes of 2^36 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes@@ this length does not include the authentication only data; the authentication length is specified in the AES_AUTH_LENGTH register below. All modes must have a length > 0. For the combined modes@@ it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine. For a Host read operation@@ these registers return all-zeroes.
DATA_IN_0	Data register to read and write plaintext/ciphertext (MSW)
DATA_IN_1	Data register to read and write plaintext/ciphertext
DATA_IN_2	Data register to read and write plaintext/ciphertext
DATA_IN_3	Data register to read and write plaintext/ciphertext (LSW)
IRQENABLE	This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_x output. All interrupts need to be enabled explicitly by writing this register. ****************************************************************************
IRQSTATUS	This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted
IV_IN_0	Initialization Vector input (LSW)
IV_IN_1	Initialization vector input
IV_IN_2	Initialization vector input
IV_IN_3	Initialization Vector input (MSW)
KEY1_0	Key (LSW for 128-bit key)
KEY1_1	Key
KEY1_2	Key
KEY1_3	Key (MSW for 128-bit key)
KEY1_4	Key (LSW for 192-bit key)
KEY1_5	Key (MSW for 192-bit key)
KEY1_6	Key (LSW for 256-bit key)
KEY1_7	Key (MSW for 256-bit key)
KEY2_0	XTS / CCM / CBC-MAC second key (LSW) / Hash Key input (LSW)
KEY2_1	XTS / CCM / CBC-MAC second key / Hash Key input
KEY2_2	XTS / CCM / CBC-MAC second key / Hash Key input
KEY2_3	XTS second key (MSW for 128-bit key) + CCM/CBC-MAC second key (MSW) / Hash Key input (MSW)
KEY2_4	XTS / CCM second key / CBC-MAC third key (LSW)
KEY2_5	XTS second key (MSW for 192-bit key) / CBC-MAC third key
KEY2_6	XTS second key / CBC-MAC third key
KEY2_7	XTS second key (MSW for 256-bit key) / CBC-MAC third key (MSW)
REVISION	Register AES_REVISION
SYSCONFIG	Register AES_SYSCONFIG.This register configures the DMA signals and controls the IDLE and reset logic
SYSSTATUS	SYSSTATUS
TAG_OUT_0	TAG_OUT_0
TAG_OUT_1	TAG_OUT_1
TAG_OUT_2	TAG_OUT_2
TAG_OUT_3	TAG_OUT_3