Struct cc2650::i2c0::mstat::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved7(&self) -> RESERVED7R

Bits 7:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn busbsy(&self) -> BUSBSYR

Bit 6 - Bus busy 0: The I2C bus is idle. 1: The I2C bus is busy. The bit changes based on the MCTRL.START and MCTRL.STOP conditions.

pub fn idle(&self) -> IDLER

Bit 5 - I2C idle 0: The I2C controller is not idle. 1: The I2C controller is idle.

pub fn arblst(&self) -> ARBLSTR

Bit 4 - Arbitration lost 0: The I2C controller won arbitration. 1: The I2C controller lost arbitration.

pub fn datack_n(&self) -> DATACK_NR

Bit 3 - Data Was Not Acknowledge 0: The transmitted data was acknowledged. 1: The transmitted data was not acknowledged.

pub fn adrack_n(&self) -> ADRACK_NR

Bit 2 - Address Was Not Acknowledge 0: The transmitted address was acknowledged. 1: The transmitted address was not acknowledged.

pub fn err(&self) -> ERRR

Bit 1 - Error 0: No error was detected on the last operation. 1: An error occurred on the last operation.

pub fn busy(&self) -> BUSYR

Bit 0 - I2C busy 0: The controller is idle. 1: The controller is busy. When this bit-field is set, the other status bits are not valid. Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been initiated through MCTRL register. Hence after programming MCTRL register, application is requested to wait for four SYSBUS clock cycles before issuing a controller status inquiry through MSTAT register. Any prior inquiry would result in wrong status being reported.