Struct cc2650::cpu_scs::dhcsr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved26(&mut self) -> _RESERVED26W

Bits 26:31 - Software should not rely on the value of a reserved. When writing to this register, 0x28 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn s_reset_st(&mut self) -> _S_RESET_STW

Bit 25 - Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn s_retire_st(&mut self) -> _S_RETIRE_STW

Bit 24 - Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn reserved20(&mut self) -> _RESERVED20W

Bits 20:23 - Software should not rely on the value of a reserved. When writing to this register, 0x5 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn s_lockup(&mut self) -> _S_LOCKUPW

Bit 19 - Reads as one if the core is running (not halted) and a lockup condition is present. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn s_sleep(&mut self) -> _S_SLEEPW

Bit 18 - Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn s_halt(&mut self) -> _S_HALTW

Bit 17 - The core is in debug state when this bit is set. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn s_regrdy(&mut self) -> _S_REGRDYW

Bit 16 - Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.

pub fn c_snapstall(&mut self) -> _C_SNAPSTALLW

Bit 5 - If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE_ST can detect core stalls on load/store operations.

pub fn reserved4(&mut self) -> _RESERVED4W

Bit 4 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn c_maskints(&mut self) -> _C_MASKINTSW

Bit 3 - Mask interrupts when stepping or running in halted debug. This masking does not affect NMI, fault exceptions and SVC caused by execution of the instructions. This bit must only be modified when the processor is halted (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate). Modifying C_MASKINTS while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior.

pub fn c_step(&mut self) -> _C_STEPW

Bit 2 - Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). Modifying C_STEP while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior.

pub fn c_halt(&mut self) -> _C_HALTW

Bit 1 - Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset.

pub fn c_debugen(&mut self) -> _C_DEBUGENW

Bit 0 - Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0.