Struct cc2650::cpu_scs::cfsr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved26(&mut self) -> _RESERVED26W

Bits 26:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn divbyzero(&mut self) -> _DIVBYZEROW

Bit 25 - When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0.

pub fn unaligned(&mut self) -> _UNALIGNEDW

Bit 24 - When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP.

pub fn reserved20(&mut self) -> _RESERVED20W

Bits 20:23 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn nocp(&mut self) -> _NOCPW

Bit 19 - Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions.

pub fn invpc(&mut self) -> _INVPCW

Bit 18 - Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.

pub fn invstate(&mut self) -> _INVSTATEW

Bit 17 - Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state.

pub fn undefinstr(&mut self) -> _UNDEFINSTRW

Bit 16 - This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.

pub fn bfarvalid(&mut self) -> _BFARVALIDW

Bit 15 - This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.

pub fn reserved13(&mut self) -> _RESERVED13W

Bits 13:14 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn stkerr(&mut self) -> _STKERRW

Bit 12 - Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written.

pub fn unstkerr(&mut self) -> _UNSTKERRW

Bit 11 - Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written.

pub fn impreciserr(&mut self) -> _IMPRECISERRW

Bit 10 - Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written.

pub fn preciserr(&mut self) -> _PRECISERRW

Bit 9 - Precise data bus error return.

pub fn ibuserr(&mut self) -> _IBUSERRW

Bit 8 - Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written.

pub fn mmarvalid(&mut self) -> _MMARVALIDW

Bit 7 - Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten.

pub fn reserved5(&mut self) -> _RESERVED5W

Bits 5:6 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn mstkerr(&mut self) -> _MSTKERRW

Bit 4 - Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written.

pub fn munstkerr(&mut self) -> _MUNSTKERRW

Bit 3 - Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written.

pub fn reserved2(&mut self) -> _RESERVED2W

Bit 2 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn daccviol(&mut self) -> _DACCVIOLW

Bit 1 - Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access.

pub fn iaccviol(&mut self) -> _IACCVIOLW

Bit 0 - Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written.