Struct cc2650::aux_adi4::adc0::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u8) -> &mut Self

Writes raw bits to the register

pub fn smpl_mode(&mut self) -> _SMPL_MODEW

Bit 7 - ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode The ADC does a sample-and-hold before conversion. In synchronous mode the sampling starts when the ADC clock detects a rising edge on the trigger signal. Jitter/uncertainty will be inferred in the detection if the trigger signal originates from a domain that is asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the the duration of sampling. Conversion starts immediately after sampling ends. In asynchronous mode the sampling is continuous when enabled. Sampling ends and conversion starts immediately with the rising edge of the trigger signal. Sampling restarts when the conversion has finished. Asynchronous mode is useful when it is important to avoid jitter in the sampling instant of an externally driven signal

pub fn smpl_cycle_exp(&mut self) -> _SMPL_CYCLE_EXPW

Bits 3:6 - Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us.

pub fn reserved2(&mut self) -> _RESERVED2W

Bit 2 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn reset_n(&mut self) -> _RESET_NW

Bit 1 - Reset ADC digital subchip, active low. ADC must be reset every time it is reconfigured. 0: Reset 1: Normal operation

pub fn en(&mut self) -> _ENW

Bit 0 - ADC Enable 0: Disable 1: Enable