cc2650/prcm/
secdmaclkgr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SECDMACLKGR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R { bits: self.register.get() }
26    }
27    #[doc = r" Writes to the register"]
28    #[inline]
29    pub fn write<F>(&self, f: F)
30    where
31        F: FnOnce(&mut W) -> &mut W,
32    {
33        let mut w = W::reset_value();
34        f(&mut w);
35        self.register.set(w.bits);
36    }
37    #[doc = r" Writes the reset value to the register"]
38    #[inline]
39    pub fn reset(&self) {
40        self.write(|w| w)
41    }
42}
43#[doc = r" Value of the field"]
44pub struct RESERVED9R {
45    bits: u32,
46}
47impl RESERVED9R {
48    #[doc = r" Value of the field as raw bits"]
49    #[inline]
50    pub fn bits(&self) -> u32 {
51        self.bits
52    }
53}
54#[doc = r" Value of the field"]
55pub struct DMA_CLK_ENR {
56    bits: bool,
57}
58impl DMA_CLK_ENR {
59    #[doc = r" Value of the field as raw bits"]
60    #[inline]
61    pub fn bit(&self) -> bool {
62        self.bits
63    }
64    #[doc = r" Returns `true` if the bit is clear (0)"]
65    #[inline]
66    pub fn bit_is_clear(&self) -> bool {
67        !self.bit()
68    }
69    #[doc = r" Returns `true` if the bit is set (1)"]
70    #[inline]
71    pub fn bit_is_set(&self) -> bool {
72        self.bit()
73    }
74}
75#[doc = r" Value of the field"]
76pub struct RESERVED2R {
77    bits: u8,
78}
79impl RESERVED2R {
80    #[doc = r" Value of the field as raw bits"]
81    #[inline]
82    pub fn bits(&self) -> u8 {
83        self.bits
84    }
85}
86#[doc = r" Value of the field"]
87pub struct TRNG_CLK_ENR {
88    bits: bool,
89}
90impl TRNG_CLK_ENR {
91    #[doc = r" Value of the field as raw bits"]
92    #[inline]
93    pub fn bit(&self) -> bool {
94        self.bits
95    }
96    #[doc = r" Returns `true` if the bit is clear (0)"]
97    #[inline]
98    pub fn bit_is_clear(&self) -> bool {
99        !self.bit()
100    }
101    #[doc = r" Returns `true` if the bit is set (1)"]
102    #[inline]
103    pub fn bit_is_set(&self) -> bool {
104        self.bit()
105    }
106}
107#[doc = r" Value of the field"]
108pub struct CRYPTO_CLK_ENR {
109    bits: bool,
110}
111impl CRYPTO_CLK_ENR {
112    #[doc = r" Value of the field as raw bits"]
113    #[inline]
114    pub fn bit(&self) -> bool {
115        self.bits
116    }
117    #[doc = r" Returns `true` if the bit is clear (0)"]
118    #[inline]
119    pub fn bit_is_clear(&self) -> bool {
120        !self.bit()
121    }
122    #[doc = r" Returns `true` if the bit is set (1)"]
123    #[inline]
124    pub fn bit_is_set(&self) -> bool {
125        self.bit()
126    }
127}
128#[doc = r" Proxy"]
129pub struct _DMA_CLK_ENW<'a> {
130    w: &'a mut W,
131}
132impl<'a> _DMA_CLK_ENW<'a> {
133    #[doc = r" Sets the field bit"]
134    pub fn set_bit(self) -> &'a mut W {
135        self.bit(true)
136    }
137    #[doc = r" Clears the field bit"]
138    pub fn clear_bit(self) -> &'a mut W {
139        self.bit(false)
140    }
141    #[doc = r" Writes raw bits to the field"]
142    #[inline]
143    pub fn bit(self, value: bool) -> &'a mut W {
144        const MASK: bool = true;
145        const OFFSET: u8 = 8;
146        self.w.bits &= !((MASK as u32) << OFFSET);
147        self.w.bits |= ((value & MASK) as u32) << OFFSET;
148        self.w
149    }
150}
151#[doc = r" Proxy"]
152pub struct _TRNG_CLK_ENW<'a> {
153    w: &'a mut W,
154}
155impl<'a> _TRNG_CLK_ENW<'a> {
156    #[doc = r" Sets the field bit"]
157    pub fn set_bit(self) -> &'a mut W {
158        self.bit(true)
159    }
160    #[doc = r" Clears the field bit"]
161    pub fn clear_bit(self) -> &'a mut W {
162        self.bit(false)
163    }
164    #[doc = r" Writes raw bits to the field"]
165    #[inline]
166    pub fn bit(self, value: bool) -> &'a mut W {
167        const MASK: bool = true;
168        const OFFSET: u8 = 1;
169        self.w.bits &= !((MASK as u32) << OFFSET);
170        self.w.bits |= ((value & MASK) as u32) << OFFSET;
171        self.w
172    }
173}
174#[doc = r" Proxy"]
175pub struct _CRYPTO_CLK_ENW<'a> {
176    w: &'a mut W,
177}
178impl<'a> _CRYPTO_CLK_ENW<'a> {
179    #[doc = r" Sets the field bit"]
180    pub fn set_bit(self) -> &'a mut W {
181        self.bit(true)
182    }
183    #[doc = r" Clears the field bit"]
184    pub fn clear_bit(self) -> &'a mut W {
185        self.bit(false)
186    }
187    #[doc = r" Writes raw bits to the field"]
188    #[inline]
189    pub fn bit(self, value: bool) -> &'a mut W {
190        const MASK: bool = true;
191        const OFFSET: u8 = 0;
192        self.w.bits &= !((MASK as u32) << OFFSET);
193        self.w.bits |= ((value & MASK) as u32) << OFFSET;
194        self.w
195    }
196}
197impl R {
198    #[doc = r" Value of the register as raw bits"]
199    #[inline]
200    pub fn bits(&self) -> u32 {
201        self.bits
202    }
203    #[doc = "Bits 9:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
204    #[inline]
205    pub fn reserved9(&self) -> RESERVED9R {
206        let bits = {
207            const MASK: u32 = 8388607;
208            const OFFSET: u8 = 9;
209            ((self.bits >> OFFSET) & MASK as u32) as u32
210        };
211        RESERVED9R { bits }
212    }
213    #[doc = "Bit 8 - 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
214    #[inline]
215    pub fn dma_clk_en(&self) -> DMA_CLK_ENR {
216        let bits = {
217            const MASK: bool = true;
218            const OFFSET: u8 = 8;
219            ((self.bits >> OFFSET) & MASK as u32) != 0
220        };
221        DMA_CLK_ENR { bits }
222    }
223    #[doc = "Bits 2:7 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
224    #[inline]
225    pub fn reserved2(&self) -> RESERVED2R {
226        let bits = {
227            const MASK: u8 = 63;
228            const OFFSET: u8 = 2;
229            ((self.bits >> OFFSET) & MASK as u32) as u8
230        };
231        RESERVED2R { bits }
232    }
233    #[doc = "Bit 1 - 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
234    #[inline]
235    pub fn trng_clk_en(&self) -> TRNG_CLK_ENR {
236        let bits = {
237            const MASK: bool = true;
238            const OFFSET: u8 = 1;
239            ((self.bits >> OFFSET) & MASK as u32) != 0
240        };
241        TRNG_CLK_ENR { bits }
242    }
243    #[doc = "Bit 0 - 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
244    #[inline]
245    pub fn crypto_clk_en(&self) -> CRYPTO_CLK_ENR {
246        let bits = {
247            const MASK: bool = true;
248            const OFFSET: u8 = 0;
249            ((self.bits >> OFFSET) & MASK as u32) != 0
250        };
251        CRYPTO_CLK_ENR { bits }
252    }
253}
254impl W {
255    #[doc = r" Reset value of the register"]
256    #[inline]
257    pub fn reset_value() -> W {
258        W { bits: 0 }
259    }
260    #[doc = r" Writes raw bits to the register"]
261    #[inline]
262    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
263        self.bits = bits;
264        self
265    }
266    #[doc = "Bit 8 - 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
267    #[inline]
268    pub fn dma_clk_en(&mut self) -> _DMA_CLK_ENW {
269        _DMA_CLK_ENW { w: self }
270    }
271    #[doc = "Bit 1 - 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
272    #[inline]
273    pub fn trng_clk_en(&mut self) -> _TRNG_CLK_ENW {
274        _TRNG_CLK_ENW { w: self }
275    }
276    #[doc = "Bit 0 - 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
277    #[inline]
278    pub fn crypto_clk_en(&mut self) -> _CRYPTO_CLK_ENW {
279        _CRYPTO_CLK_ENW { w: self }
280    }
281}
cc2650/prcm/secdmaclkgr.rs

cc2650/prcm/
secdmaclkgr.rs
