1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::IOCFG21 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R { bits: self.register.get() }
26 }
27 #[doc = r" Writes to the register"]
28 #[inline]
29 pub fn write<F>(&self, f: F)
30 where
31 F: FnOnce(&mut W) -> &mut W,
32 {
33 let mut w = W::reset_value();
34 f(&mut w);
35 self.register.set(w.bits);
36 }
37 #[doc = r" Writes the reset value to the register"]
38 #[inline]
39 pub fn reset(&self) {
40 self.write(|w| w)
41 }
42}
43#[doc = r" Value of the field"]
44pub struct RESERVED31R {
45 bits: bool,
46}
47impl RESERVED31R {
48 #[doc = r" Value of the field as raw bits"]
49 #[inline]
50 pub fn bit(&self) -> bool {
51 self.bits
52 }
53 #[doc = r" Returns `true` if the bit is clear (0)"]
54 #[inline]
55 pub fn bit_is_clear(&self) -> bool {
56 !self.bit()
57 }
58 #[doc = r" Returns `true` if the bit is set (1)"]
59 #[inline]
60 pub fn bit_is_set(&self) -> bool {
61 self.bit()
62 }
63}
64#[doc = r" Value of the field"]
65pub struct HYST_ENR {
66 bits: bool,
67}
68impl HYST_ENR {
69 #[doc = r" Value of the field as raw bits"]
70 #[inline]
71 pub fn bit(&self) -> bool {
72 self.bits
73 }
74 #[doc = r" Returns `true` if the bit is clear (0)"]
75 #[inline]
76 pub fn bit_is_clear(&self) -> bool {
77 !self.bit()
78 }
79 #[doc = r" Returns `true` if the bit is set (1)"]
80 #[inline]
81 pub fn bit_is_set(&self) -> bool {
82 self.bit()
83 }
84}
85#[doc = r" Value of the field"]
86pub struct IER {
87 bits: bool,
88}
89impl IER {
90 #[doc = r" Value of the field as raw bits"]
91 #[inline]
92 pub fn bit(&self) -> bool {
93 self.bits
94 }
95 #[doc = r" Returns `true` if the bit is clear (0)"]
96 #[inline]
97 pub fn bit_is_clear(&self) -> bool {
98 !self.bit()
99 }
100 #[doc = r" Returns `true` if the bit is set (1)"]
101 #[inline]
102 pub fn bit_is_set(&self) -> bool {
103 self.bit()
104 }
105}
106#[doc = r" Value of the field"]
107pub struct WU_CFGR {
108 bits: u8,
109}
110impl WU_CFGR {
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bits(&self) -> u8 {
114 self.bits
115 }
116}
117#[doc = "Possible values of the field `IOMODE`"]
118#[derive(Clone, Copy, Debug, PartialEq)]
119pub enum IOMODER {
120 #[doc = "Open Source\nInverted input / output\n\n"]
121 OPENSRC_INV,
122 #[doc = "Open Source\nNormal input / output\n\n"]
123 OPENSRC,
124 #[doc = "Open Drain\nInverted input / output\n\n"]
125 OPENDR_INV,
126 #[doc = "Open Drain, \nNormal input / output\n\n"]
127 OPENDR,
128 #[doc = "Inverted input / ouput\n\n"]
129 INV,
130 #[doc = "Normal input / output\n\n"]
131 NORMAL,
132 #[doc = r" Reserved"]
133 _Reserved(u8),
134}
135impl IOMODER {
136 #[doc = r" Value of the field as raw bits"]
137 #[inline]
138 pub fn bits(&self) -> u8 {
139 match *self {
140 IOMODER::OPENSRC_INV => 7,
141 IOMODER::OPENSRC => 6,
142 IOMODER::OPENDR_INV => 5,
143 IOMODER::OPENDR => 4,
144 IOMODER::INV => 1,
145 IOMODER::NORMAL => 0,
146 IOMODER::_Reserved(bits) => bits,
147 }
148 }
149 #[allow(missing_docs)]
150 #[doc(hidden)]
151 #[inline]
152 pub fn _from(value: u8) -> IOMODER {
153 match value {
154 7 => IOMODER::OPENSRC_INV,
155 6 => IOMODER::OPENSRC,
156 5 => IOMODER::OPENDR_INV,
157 4 => IOMODER::OPENDR,
158 1 => IOMODER::INV,
159 0 => IOMODER::NORMAL,
160 i => IOMODER::_Reserved(i),
161 }
162 }
163 #[doc = "Checks if the value of the field is `OPENSRC_INV`"]
164 #[inline]
165 pub fn is_opensrc_inv(&self) -> bool {
166 *self == IOMODER::OPENSRC_INV
167 }
168 #[doc = "Checks if the value of the field is `OPENSRC`"]
169 #[inline]
170 pub fn is_opensrc(&self) -> bool {
171 *self == IOMODER::OPENSRC
172 }
173 #[doc = "Checks if the value of the field is `OPENDR_INV`"]
174 #[inline]
175 pub fn is_opendr_inv(&self) -> bool {
176 *self == IOMODER::OPENDR_INV
177 }
178 #[doc = "Checks if the value of the field is `OPENDR`"]
179 #[inline]
180 pub fn is_opendr(&self) -> bool {
181 *self == IOMODER::OPENDR
182 }
183 #[doc = "Checks if the value of the field is `INV`"]
184 #[inline]
185 pub fn is_inv(&self) -> bool {
186 *self == IOMODER::INV
187 }
188 #[doc = "Checks if the value of the field is `NORMAL`"]
189 #[inline]
190 pub fn is_normal(&self) -> bool {
191 *self == IOMODER::NORMAL
192 }
193}
194#[doc = r" Value of the field"]
195pub struct RESERVED19R {
196 bits: u8,
197}
198impl RESERVED19R {
199 #[doc = r" Value of the field as raw bits"]
200 #[inline]
201 pub fn bits(&self) -> u8 {
202 self.bits
203 }
204}
205#[doc = r" Value of the field"]
206pub struct EDGE_IRQ_ENR {
207 bits: bool,
208}
209impl EDGE_IRQ_ENR {
210 #[doc = r" Value of the field as raw bits"]
211 #[inline]
212 pub fn bit(&self) -> bool {
213 self.bits
214 }
215 #[doc = r" Returns `true` if the bit is clear (0)"]
216 #[inline]
217 pub fn bit_is_clear(&self) -> bool {
218 !self.bit()
219 }
220 #[doc = r" Returns `true` if the bit is set (1)"]
221 #[inline]
222 pub fn bit_is_set(&self) -> bool {
223 self.bit()
224 }
225}
226#[doc = "Possible values of the field `EDGE_DET`"]
227#[derive(Clone, Copy, Debug, PartialEq)]
228pub enum EDGE_DETR {
229 #[doc = "Positive and negative edge detection"]
230 BOTH,
231 #[doc = "Positive edge detection"]
232 POS,
233 #[doc = "Negative edge detection"]
234 NEG,
235 #[doc = "No edge detection"]
236 NONE,
237}
238impl EDGE_DETR {
239 #[doc = r" Value of the field as raw bits"]
240 #[inline]
241 pub fn bits(&self) -> u8 {
242 match *self {
243 EDGE_DETR::BOTH => 3,
244 EDGE_DETR::POS => 2,
245 EDGE_DETR::NEG => 1,
246 EDGE_DETR::NONE => 0,
247 }
248 }
249 #[allow(missing_docs)]
250 #[doc(hidden)]
251 #[inline]
252 pub fn _from(value: u8) -> EDGE_DETR {
253 match value {
254 3 => EDGE_DETR::BOTH,
255 2 => EDGE_DETR::POS,
256 1 => EDGE_DETR::NEG,
257 0 => EDGE_DETR::NONE,
258 _ => unreachable!(),
259 }
260 }
261 #[doc = "Checks if the value of the field is `BOTH`"]
262 #[inline]
263 pub fn is_both(&self) -> bool {
264 *self == EDGE_DETR::BOTH
265 }
266 #[doc = "Checks if the value of the field is `POS`"]
267 #[inline]
268 pub fn is_pos(&self) -> bool {
269 *self == EDGE_DETR::POS
270 }
271 #[doc = "Checks if the value of the field is `NEG`"]
272 #[inline]
273 pub fn is_neg(&self) -> bool {
274 *self == EDGE_DETR::NEG
275 }
276 #[doc = "Checks if the value of the field is `NONE`"]
277 #[inline]
278 pub fn is_none(&self) -> bool {
279 *self == EDGE_DETR::NONE
280 }
281}
282#[doc = r" Value of the field"]
283pub struct RESERVED15R {
284 bits: bool,
285}
286impl RESERVED15R {
287 #[doc = r" Value of the field as raw bits"]
288 #[inline]
289 pub fn bit(&self) -> bool {
290 self.bits
291 }
292 #[doc = r" Returns `true` if the bit is clear (0)"]
293 #[inline]
294 pub fn bit_is_clear(&self) -> bool {
295 !self.bit()
296 }
297 #[doc = r" Returns `true` if the bit is set (1)"]
298 #[inline]
299 pub fn bit_is_set(&self) -> bool {
300 self.bit()
301 }
302}
303#[doc = "Possible values of the field `PULL_CTL`"]
304#[derive(Clone, Copy, Debug, PartialEq)]
305pub enum PULL_CTLR {
306 #[doc = "No pull"]
307 DIS,
308 #[doc = "Pull up"]
309 UP,
310 #[doc = "Pull down"]
311 DWN,
312 #[doc = r" Reserved"]
313 _Reserved(u8),
314}
315impl PULL_CTLR {
316 #[doc = r" Value of the field as raw bits"]
317 #[inline]
318 pub fn bits(&self) -> u8 {
319 match *self {
320 PULL_CTLR::DIS => 3,
321 PULL_CTLR::UP => 2,
322 PULL_CTLR::DWN => 1,
323 PULL_CTLR::_Reserved(bits) => bits,
324 }
325 }
326 #[allow(missing_docs)]
327 #[doc(hidden)]
328 #[inline]
329 pub fn _from(value: u8) -> PULL_CTLR {
330 match value {
331 3 => PULL_CTLR::DIS,
332 2 => PULL_CTLR::UP,
333 1 => PULL_CTLR::DWN,
334 i => PULL_CTLR::_Reserved(i),
335 }
336 }
337 #[doc = "Checks if the value of the field is `DIS`"]
338 #[inline]
339 pub fn is_dis(&self) -> bool {
340 *self == PULL_CTLR::DIS
341 }
342 #[doc = "Checks if the value of the field is `UP`"]
343 #[inline]
344 pub fn is_up(&self) -> bool {
345 *self == PULL_CTLR::UP
346 }
347 #[doc = "Checks if the value of the field is `DWN`"]
348 #[inline]
349 pub fn is_dwn(&self) -> bool {
350 *self == PULL_CTLR::DWN
351 }
352}
353#[doc = r" Value of the field"]
354pub struct SLEW_REDR {
355 bits: bool,
356}
357impl SLEW_REDR {
358 #[doc = r" Value of the field as raw bits"]
359 #[inline]
360 pub fn bit(&self) -> bool {
361 self.bits
362 }
363 #[doc = r" Returns `true` if the bit is clear (0)"]
364 #[inline]
365 pub fn bit_is_clear(&self) -> bool {
366 !self.bit()
367 }
368 #[doc = r" Returns `true` if the bit is set (1)"]
369 #[inline]
370 pub fn bit_is_set(&self) -> bool {
371 self.bit()
372 }
373}
374#[doc = "Possible values of the field `IOCURR`"]
375#[derive(Clone, Copy, Debug, PartialEq)]
376pub enum IOCURRR {
377 #[doc = "Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO"]
378 _4_8MA,
379 #[doc = "High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO"]
380 _4MA,
381 #[doc = "Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO"]
382 _2MA,
383 #[doc = r" Reserved"]
384 _Reserved(u8),
385}
386impl IOCURRR {
387 #[doc = r" Value of the field as raw bits"]
388 #[inline]
389 pub fn bits(&self) -> u8 {
390 match *self {
391 IOCURRR::_4_8MA => 2,
392 IOCURRR::_4MA => 1,
393 IOCURRR::_2MA => 0,
394 IOCURRR::_Reserved(bits) => bits,
395 }
396 }
397 #[allow(missing_docs)]
398 #[doc(hidden)]
399 #[inline]
400 pub fn _from(value: u8) -> IOCURRR {
401 match value {
402 2 => IOCURRR::_4_8MA,
403 1 => IOCURRR::_4MA,
404 0 => IOCURRR::_2MA,
405 i => IOCURRR::_Reserved(i),
406 }
407 }
408 #[doc = "Checks if the value of the field is `_4_8MA`"]
409 #[inline]
410 pub fn is_4_8ma(&self) -> bool {
411 *self == IOCURRR::_4_8MA
412 }
413 #[doc = "Checks if the value of the field is `_4MA`"]
414 #[inline]
415 pub fn is_4ma(&self) -> bool {
416 *self == IOCURRR::_4MA
417 }
418 #[doc = "Checks if the value of the field is `_2MA`"]
419 #[inline]
420 pub fn is_2ma(&self) -> bool {
421 *self == IOCURRR::_2MA
422 }
423}
424#[doc = "Possible values of the field `IOSTR`"]
425#[derive(Clone, Copy, Debug, PartialEq)]
426pub enum IOSTRR {
427 #[doc = "Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)"]
428 MAX,
429 #[doc = "Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)"]
430 MED,
431 #[doc = "Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)"]
432 MIN,
433 #[doc = "Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)"]
434 AUTO,
435}
436impl IOSTRR {
437 #[doc = r" Value of the field as raw bits"]
438 #[inline]
439 pub fn bits(&self) -> u8 {
440 match *self {
441 IOSTRR::MAX => 3,
442 IOSTRR::MED => 2,
443 IOSTRR::MIN => 1,
444 IOSTRR::AUTO => 0,
445 }
446 }
447 #[allow(missing_docs)]
448 #[doc(hidden)]
449 #[inline]
450 pub fn _from(value: u8) -> IOSTRR {
451 match value {
452 3 => IOSTRR::MAX,
453 2 => IOSTRR::MED,
454 1 => IOSTRR::MIN,
455 0 => IOSTRR::AUTO,
456 _ => unreachable!(),
457 }
458 }
459 #[doc = "Checks if the value of the field is `MAX`"]
460 #[inline]
461 pub fn is_max(&self) -> bool {
462 *self == IOSTRR::MAX
463 }
464 #[doc = "Checks if the value of the field is `MED`"]
465 #[inline]
466 pub fn is_med(&self) -> bool {
467 *self == IOSTRR::MED
468 }
469 #[doc = "Checks if the value of the field is `MIN`"]
470 #[inline]
471 pub fn is_min(&self) -> bool {
472 *self == IOSTRR::MIN
473 }
474 #[doc = "Checks if the value of the field is `AUTO`"]
475 #[inline]
476 pub fn is_auto(&self) -> bool {
477 *self == IOSTRR::AUTO
478 }
479}
480#[doc = r" Value of the field"]
481pub struct RESERVED6R {
482 bits: u8,
483}
484impl RESERVED6R {
485 #[doc = r" Value of the field as raw bits"]
486 #[inline]
487 pub fn bits(&self) -> u8 {
488 self.bits
489 }
490}
491#[doc = "Possible values of the field `PORT_ID`"]
492#[derive(Clone, Copy, Debug, PartialEq)]
493pub enum PORT_IDR {
494 #[doc = "RF Core SMI Command Link In"]
495 RFC_SMI_CL_IN,
496 #[doc = "RF Core SMI Command Link Out"]
497 RFC_SMI_CL_OUT,
498 #[doc = "RF Core SMI Data Link In"]
499 RFC_SMI_DL_IN,
500 #[doc = "RF Core SMI Data Link Out"]
501 RFC_SMI_DL_OUT,
502 #[doc = "RF Core Data In 1"]
503 RFC_GPI1,
504 #[doc = "RF Core Data In 0"]
505 RFC_GPI0,
506 #[doc = "RF Core Data Out 3"]
507 RFC_GPO3,
508 #[doc = "RF Core Data Out 2"]
509 RFC_GPO2,
510 #[doc = "RF Core Data Out 1"]
511 RFC_GPO1,
512 #[doc = "RF Core Data Out 0"]
513 RFC_GPO0,
514 #[doc = "RF Core Trace"]
515 RFC_TRC,
516 #[doc = "I2S MCLK "]
517 I2S_MCLK,
518 #[doc = "I2S BCLK "]
519 I2S_BCLK,
520 #[doc = "I2S WCLK "]
521 I2S_WCLK,
522 #[doc = "I2S Data 1"]
523 I2S_AD1,
524 #[doc = "I2S Data 0"]
525 I2S_AD0,
526 #[doc = "SSI1 CLK"]
527 SSI1_CLK,
528 #[doc = "SSI1 FSS "]
529 SSI1_FSS,
530 #[doc = "SSI1 TX "]
531 SSI1_TX,
532 #[doc = "SSI1 RX "]
533 SSI1_RX,
534 #[doc = "CPU SWV "]
535 CPU_SWV,
536 #[doc = "PORT EVENT 7\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
537 PORT_EVENT7,
538 #[doc = "PORT EVENT 6\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
539 PORT_EVENT6,
540 #[doc = "PORT EVENT 5\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
541 PORT_EVENT5,
542 #[doc = "PORT EVENT 4\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
543 PORT_EVENT4,
544 #[doc = "PORT EVENT 3\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
545 PORT_EVENT3,
546 #[doc = "PORT EVENT 2\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
547 PORT_EVENT2,
548 #[doc = "PORT EVENT 1\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
549 PORT_EVENT1,
550 #[doc = "PORT EVENT 0\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
551 PORT_EVENT0,
552 #[doc = "UART0 RTS "]
553 UART0_RTS,
554 #[doc = "UART0 CTS "]
555 UART0_CTS,
556 #[doc = "UART0 TX "]
557 UART0_TX,
558 #[doc = "UART0 RX "]
559 UART0_RX,
560 #[doc = "I2C Clock"]
561 I2C_MSSCL,
562 #[doc = "I2C Data"]
563 I2C_MSSDA,
564 #[doc = "SSI0 CLK"]
565 SSI0_CLK,
566 #[doc = "SSI0 FSS "]
567 SSI0_FSS,
568 #[doc = "SSI0 TX "]
569 SSI0_TX,
570 #[doc = "SSI0 RX "]
571 SSI0_RX,
572 #[doc = "AUX IO "]
573 AUX_IO,
574 #[doc = "AON 32 KHz clock (SCLK_LF)"]
575 AON_CLK32K,
576 #[doc = "General Purpose IO "]
577 GPIO,
578 #[doc = r" Reserved"]
579 _Reserved(u8),
580}
581impl PORT_IDR {
582 #[doc = r" Value of the field as raw bits"]
583 #[inline]
584 pub fn bits(&self) -> u8 {
585 match *self {
586 PORT_IDR::RFC_SMI_CL_IN => 56,
587 PORT_IDR::RFC_SMI_CL_OUT => 55,
588 PORT_IDR::RFC_SMI_DL_IN => 54,
589 PORT_IDR::RFC_SMI_DL_OUT => 53,
590 PORT_IDR::RFC_GPI1 => 52,
591 PORT_IDR::RFC_GPI0 => 51,
592 PORT_IDR::RFC_GPO3 => 50,
593 PORT_IDR::RFC_GPO2 => 49,
594 PORT_IDR::RFC_GPO1 => 48,
595 PORT_IDR::RFC_GPO0 => 47,
596 PORT_IDR::RFC_TRC => 46,
597 PORT_IDR::I2S_MCLK => 41,
598 PORT_IDR::I2S_BCLK => 40,
599 PORT_IDR::I2S_WCLK => 39,
600 PORT_IDR::I2S_AD1 => 38,
601 PORT_IDR::I2S_AD0 => 37,
602 PORT_IDR::SSI1_CLK => 36,
603 PORT_IDR::SSI1_FSS => 35,
604 PORT_IDR::SSI1_TX => 34,
605 PORT_IDR::SSI1_RX => 33,
606 PORT_IDR::CPU_SWV => 32,
607 PORT_IDR::PORT_EVENT7 => 30,
608 PORT_IDR::PORT_EVENT6 => 29,
609 PORT_IDR::PORT_EVENT5 => 28,
610 PORT_IDR::PORT_EVENT4 => 27,
611 PORT_IDR::PORT_EVENT3 => 26,
612 PORT_IDR::PORT_EVENT2 => 25,
613 PORT_IDR::PORT_EVENT1 => 24,
614 PORT_IDR::PORT_EVENT0 => 23,
615 PORT_IDR::UART0_RTS => 18,
616 PORT_IDR::UART0_CTS => 17,
617 PORT_IDR::UART0_TX => 16,
618 PORT_IDR::UART0_RX => 15,
619 PORT_IDR::I2C_MSSCL => 14,
620 PORT_IDR::I2C_MSSDA => 13,
621 PORT_IDR::SSI0_CLK => 12,
622 PORT_IDR::SSI0_FSS => 11,
623 PORT_IDR::SSI0_TX => 10,
624 PORT_IDR::SSI0_RX => 9,
625 PORT_IDR::AUX_IO => 8,
626 PORT_IDR::AON_CLK32K => 7,
627 PORT_IDR::GPIO => 0,
628 PORT_IDR::_Reserved(bits) => bits,
629 }
630 }
631 #[allow(missing_docs)]
632 #[doc(hidden)]
633 #[inline]
634 pub fn _from(value: u8) -> PORT_IDR {
635 match value {
636 56 => PORT_IDR::RFC_SMI_CL_IN,
637 55 => PORT_IDR::RFC_SMI_CL_OUT,
638 54 => PORT_IDR::RFC_SMI_DL_IN,
639 53 => PORT_IDR::RFC_SMI_DL_OUT,
640 52 => PORT_IDR::RFC_GPI1,
641 51 => PORT_IDR::RFC_GPI0,
642 50 => PORT_IDR::RFC_GPO3,
643 49 => PORT_IDR::RFC_GPO2,
644 48 => PORT_IDR::RFC_GPO1,
645 47 => PORT_IDR::RFC_GPO0,
646 46 => PORT_IDR::RFC_TRC,
647 41 => PORT_IDR::I2S_MCLK,
648 40 => PORT_IDR::I2S_BCLK,
649 39 => PORT_IDR::I2S_WCLK,
650 38 => PORT_IDR::I2S_AD1,
651 37 => PORT_IDR::I2S_AD0,
652 36 => PORT_IDR::SSI1_CLK,
653 35 => PORT_IDR::SSI1_FSS,
654 34 => PORT_IDR::SSI1_TX,
655 33 => PORT_IDR::SSI1_RX,
656 32 => PORT_IDR::CPU_SWV,
657 30 => PORT_IDR::PORT_EVENT7,
658 29 => PORT_IDR::PORT_EVENT6,
659 28 => PORT_IDR::PORT_EVENT5,
660 27 => PORT_IDR::PORT_EVENT4,
661 26 => PORT_IDR::PORT_EVENT3,
662 25 => PORT_IDR::PORT_EVENT2,
663 24 => PORT_IDR::PORT_EVENT1,
664 23 => PORT_IDR::PORT_EVENT0,
665 18 => PORT_IDR::UART0_RTS,
666 17 => PORT_IDR::UART0_CTS,
667 16 => PORT_IDR::UART0_TX,
668 15 => PORT_IDR::UART0_RX,
669 14 => PORT_IDR::I2C_MSSCL,
670 13 => PORT_IDR::I2C_MSSDA,
671 12 => PORT_IDR::SSI0_CLK,
672 11 => PORT_IDR::SSI0_FSS,
673 10 => PORT_IDR::SSI0_TX,
674 9 => PORT_IDR::SSI0_RX,
675 8 => PORT_IDR::AUX_IO,
676 7 => PORT_IDR::AON_CLK32K,
677 0 => PORT_IDR::GPIO,
678 i => PORT_IDR::_Reserved(i),
679 }
680 }
681 #[doc = "Checks if the value of the field is `RFC_SMI_CL_IN`"]
682 #[inline]
683 pub fn is_rfc_smi_cl_in(&self) -> bool {
684 *self == PORT_IDR::RFC_SMI_CL_IN
685 }
686 #[doc = "Checks if the value of the field is `RFC_SMI_CL_OUT`"]
687 #[inline]
688 pub fn is_rfc_smi_cl_out(&self) -> bool {
689 *self == PORT_IDR::RFC_SMI_CL_OUT
690 }
691 #[doc = "Checks if the value of the field is `RFC_SMI_DL_IN`"]
692 #[inline]
693 pub fn is_rfc_smi_dl_in(&self) -> bool {
694 *self == PORT_IDR::RFC_SMI_DL_IN
695 }
696 #[doc = "Checks if the value of the field is `RFC_SMI_DL_OUT`"]
697 #[inline]
698 pub fn is_rfc_smi_dl_out(&self) -> bool {
699 *self == PORT_IDR::RFC_SMI_DL_OUT
700 }
701 #[doc = "Checks if the value of the field is `RFC_GPI1`"]
702 #[inline]
703 pub fn is_rfc_gpi1(&self) -> bool {
704 *self == PORT_IDR::RFC_GPI1
705 }
706 #[doc = "Checks if the value of the field is `RFC_GPI0`"]
707 #[inline]
708 pub fn is_rfc_gpi0(&self) -> bool {
709 *self == PORT_IDR::RFC_GPI0
710 }
711 #[doc = "Checks if the value of the field is `RFC_GPO3`"]
712 #[inline]
713 pub fn is_rfc_gpo3(&self) -> bool {
714 *self == PORT_IDR::RFC_GPO3
715 }
716 #[doc = "Checks if the value of the field is `RFC_GPO2`"]
717 #[inline]
718 pub fn is_rfc_gpo2(&self) -> bool {
719 *self == PORT_IDR::RFC_GPO2
720 }
721 #[doc = "Checks if the value of the field is `RFC_GPO1`"]
722 #[inline]
723 pub fn is_rfc_gpo1(&self) -> bool {
724 *self == PORT_IDR::RFC_GPO1
725 }
726 #[doc = "Checks if the value of the field is `RFC_GPO0`"]
727 #[inline]
728 pub fn is_rfc_gpo0(&self) -> bool {
729 *self == PORT_IDR::RFC_GPO0
730 }
731 #[doc = "Checks if the value of the field is `RFC_TRC`"]
732 #[inline]
733 pub fn is_rfc_trc(&self) -> bool {
734 *self == PORT_IDR::RFC_TRC
735 }
736 #[doc = "Checks if the value of the field is `I2S_MCLK`"]
737 #[inline]
738 pub fn is_i2s_mclk(&self) -> bool {
739 *self == PORT_IDR::I2S_MCLK
740 }
741 #[doc = "Checks if the value of the field is `I2S_BCLK`"]
742 #[inline]
743 pub fn is_i2s_bclk(&self) -> bool {
744 *self == PORT_IDR::I2S_BCLK
745 }
746 #[doc = "Checks if the value of the field is `I2S_WCLK`"]
747 #[inline]
748 pub fn is_i2s_wclk(&self) -> bool {
749 *self == PORT_IDR::I2S_WCLK
750 }
751 #[doc = "Checks if the value of the field is `I2S_AD1`"]
752 #[inline]
753 pub fn is_i2s_ad1(&self) -> bool {
754 *self == PORT_IDR::I2S_AD1
755 }
756 #[doc = "Checks if the value of the field is `I2S_AD0`"]
757 #[inline]
758 pub fn is_i2s_ad0(&self) -> bool {
759 *self == PORT_IDR::I2S_AD0
760 }
761 #[doc = "Checks if the value of the field is `SSI1_CLK`"]
762 #[inline]
763 pub fn is_ssi1_clk(&self) -> bool {
764 *self == PORT_IDR::SSI1_CLK
765 }
766 #[doc = "Checks if the value of the field is `SSI1_FSS`"]
767 #[inline]
768 pub fn is_ssi1_fss(&self) -> bool {
769 *self == PORT_IDR::SSI1_FSS
770 }
771 #[doc = "Checks if the value of the field is `SSI1_TX`"]
772 #[inline]
773 pub fn is_ssi1_tx(&self) -> bool {
774 *self == PORT_IDR::SSI1_TX
775 }
776 #[doc = "Checks if the value of the field is `SSI1_RX`"]
777 #[inline]
778 pub fn is_ssi1_rx(&self) -> bool {
779 *self == PORT_IDR::SSI1_RX
780 }
781 #[doc = "Checks if the value of the field is `CPU_SWV`"]
782 #[inline]
783 pub fn is_cpu_swv(&self) -> bool {
784 *self == PORT_IDR::CPU_SWV
785 }
786 #[doc = "Checks if the value of the field is `PORT_EVENT7`"]
787 #[inline]
788 pub fn is_port_event7(&self) -> bool {
789 *self == PORT_IDR::PORT_EVENT7
790 }
791 #[doc = "Checks if the value of the field is `PORT_EVENT6`"]
792 #[inline]
793 pub fn is_port_event6(&self) -> bool {
794 *self == PORT_IDR::PORT_EVENT6
795 }
796 #[doc = "Checks if the value of the field is `PORT_EVENT5`"]
797 #[inline]
798 pub fn is_port_event5(&self) -> bool {
799 *self == PORT_IDR::PORT_EVENT5
800 }
801 #[doc = "Checks if the value of the field is `PORT_EVENT4`"]
802 #[inline]
803 pub fn is_port_event4(&self) -> bool {
804 *self == PORT_IDR::PORT_EVENT4
805 }
806 #[doc = "Checks if the value of the field is `PORT_EVENT3`"]
807 #[inline]
808 pub fn is_port_event3(&self) -> bool {
809 *self == PORT_IDR::PORT_EVENT3
810 }
811 #[doc = "Checks if the value of the field is `PORT_EVENT2`"]
812 #[inline]
813 pub fn is_port_event2(&self) -> bool {
814 *self == PORT_IDR::PORT_EVENT2
815 }
816 #[doc = "Checks if the value of the field is `PORT_EVENT1`"]
817 #[inline]
818 pub fn is_port_event1(&self) -> bool {
819 *self == PORT_IDR::PORT_EVENT1
820 }
821 #[doc = "Checks if the value of the field is `PORT_EVENT0`"]
822 #[inline]
823 pub fn is_port_event0(&self) -> bool {
824 *self == PORT_IDR::PORT_EVENT0
825 }
826 #[doc = "Checks if the value of the field is `UART0_RTS`"]
827 #[inline]
828 pub fn is_uart0_rts(&self) -> bool {
829 *self == PORT_IDR::UART0_RTS
830 }
831 #[doc = "Checks if the value of the field is `UART0_CTS`"]
832 #[inline]
833 pub fn is_uart0_cts(&self) -> bool {
834 *self == PORT_IDR::UART0_CTS
835 }
836 #[doc = "Checks if the value of the field is `UART0_TX`"]
837 #[inline]
838 pub fn is_uart0_tx(&self) -> bool {
839 *self == PORT_IDR::UART0_TX
840 }
841 #[doc = "Checks if the value of the field is `UART0_RX`"]
842 #[inline]
843 pub fn is_uart0_rx(&self) -> bool {
844 *self == PORT_IDR::UART0_RX
845 }
846 #[doc = "Checks if the value of the field is `I2C_MSSCL`"]
847 #[inline]
848 pub fn is_i2c_msscl(&self) -> bool {
849 *self == PORT_IDR::I2C_MSSCL
850 }
851 #[doc = "Checks if the value of the field is `I2C_MSSDA`"]
852 #[inline]
853 pub fn is_i2c_mssda(&self) -> bool {
854 *self == PORT_IDR::I2C_MSSDA
855 }
856 #[doc = "Checks if the value of the field is `SSI0_CLK`"]
857 #[inline]
858 pub fn is_ssi0_clk(&self) -> bool {
859 *self == PORT_IDR::SSI0_CLK
860 }
861 #[doc = "Checks if the value of the field is `SSI0_FSS`"]
862 #[inline]
863 pub fn is_ssi0_fss(&self) -> bool {
864 *self == PORT_IDR::SSI0_FSS
865 }
866 #[doc = "Checks if the value of the field is `SSI0_TX`"]
867 #[inline]
868 pub fn is_ssi0_tx(&self) -> bool {
869 *self == PORT_IDR::SSI0_TX
870 }
871 #[doc = "Checks if the value of the field is `SSI0_RX`"]
872 #[inline]
873 pub fn is_ssi0_rx(&self) -> bool {
874 *self == PORT_IDR::SSI0_RX
875 }
876 #[doc = "Checks if the value of the field is `AUX_IO`"]
877 #[inline]
878 pub fn is_aux_io(&self) -> bool {
879 *self == PORT_IDR::AUX_IO
880 }
881 #[doc = "Checks if the value of the field is `AON_CLK32K`"]
882 #[inline]
883 pub fn is_aon_clk32k(&self) -> bool {
884 *self == PORT_IDR::AON_CLK32K
885 }
886 #[doc = "Checks if the value of the field is `GPIO`"]
887 #[inline]
888 pub fn is_gpio(&self) -> bool {
889 *self == PORT_IDR::GPIO
890 }
891}
892#[doc = r" Proxy"]
893pub struct _HYST_ENW<'a> {
894 w: &'a mut W,
895}
896impl<'a> _HYST_ENW<'a> {
897 #[doc = r" Sets the field bit"]
898 pub fn set_bit(self) -> &'a mut W {
899 self.bit(true)
900 }
901 #[doc = r" Clears the field bit"]
902 pub fn clear_bit(self) -> &'a mut W {
903 self.bit(false)
904 }
905 #[doc = r" Writes raw bits to the field"]
906 #[inline]
907 pub fn bit(self, value: bool) -> &'a mut W {
908 const MASK: bool = true;
909 const OFFSET: u8 = 30;
910 self.w.bits &= !((MASK as u32) << OFFSET);
911 self.w.bits |= ((value & MASK) as u32) << OFFSET;
912 self.w
913 }
914}
915#[doc = r" Proxy"]
916pub struct _IEW<'a> {
917 w: &'a mut W,
918}
919impl<'a> _IEW<'a> {
920 #[doc = r" Sets the field bit"]
921 pub fn set_bit(self) -> &'a mut W {
922 self.bit(true)
923 }
924 #[doc = r" Clears the field bit"]
925 pub fn clear_bit(self) -> &'a mut W {
926 self.bit(false)
927 }
928 #[doc = r" Writes raw bits to the field"]
929 #[inline]
930 pub fn bit(self, value: bool) -> &'a mut W {
931 const MASK: bool = true;
932 const OFFSET: u8 = 29;
933 self.w.bits &= !((MASK as u32) << OFFSET);
934 self.w.bits |= ((value & MASK) as u32) << OFFSET;
935 self.w
936 }
937}
938#[doc = r" Proxy"]
939pub struct _WU_CFGW<'a> {
940 w: &'a mut W,
941}
942impl<'a> _WU_CFGW<'a> {
943 #[doc = r" Writes raw bits to the field"]
944 #[inline]
945 pub unsafe fn bits(self, value: u8) -> &'a mut W {
946 const MASK: u8 = 3;
947 const OFFSET: u8 = 27;
948 self.w.bits &= !((MASK as u32) << OFFSET);
949 self.w.bits |= ((value & MASK) as u32) << OFFSET;
950 self.w
951 }
952}
953#[doc = "Values that can be written to the field `IOMODE`"]
954#[derive(Clone, Copy, Debug, PartialEq)]
955pub enum IOMODEW {
956 #[doc = "Open Source\nInverted input / output\n\n"]
957 OPENSRC_INV,
958 #[doc = "Open Source\nNormal input / output\n\n"]
959 OPENSRC,
960 #[doc = "Open Drain\nInverted input / output\n\n"]
961 OPENDR_INV,
962 #[doc = "Open Drain, \nNormal input / output\n\n"]
963 OPENDR,
964 #[doc = "Inverted input / ouput\n\n"]
965 INV,
966 #[doc = "Normal input / output\n\n"]
967 NORMAL,
968}
969impl IOMODEW {
970 #[allow(missing_docs)]
971 #[doc(hidden)]
972 #[inline]
973 pub fn _bits(&self) -> u8 {
974 match *self {
975 IOMODEW::OPENSRC_INV => 7,
976 IOMODEW::OPENSRC => 6,
977 IOMODEW::OPENDR_INV => 5,
978 IOMODEW::OPENDR => 4,
979 IOMODEW::INV => 1,
980 IOMODEW::NORMAL => 0,
981 }
982 }
983}
984#[doc = r" Proxy"]
985pub struct _IOMODEW<'a> {
986 w: &'a mut W,
987}
988impl<'a> _IOMODEW<'a> {
989 #[doc = r" Writes `variant` to the field"]
990 #[inline]
991 pub fn variant(self, variant: IOMODEW) -> &'a mut W {
992 unsafe { self.bits(variant._bits()) }
993 }
994 #[doc = "Open Source Inverted input / output"]
995 #[inline]
996 pub fn opensrc_inv(self) -> &'a mut W {
997 self.variant(IOMODEW::OPENSRC_INV)
998 }
999 #[doc = "Open Source Normal input / output"]
1000 #[inline]
1001 pub fn opensrc(self) -> &'a mut W {
1002 self.variant(IOMODEW::OPENSRC)
1003 }
1004 #[doc = "Open Drain Inverted input / output"]
1005 #[inline]
1006 pub fn opendr_inv(self) -> &'a mut W {
1007 self.variant(IOMODEW::OPENDR_INV)
1008 }
1009 #[doc = "Open Drain, Normal input / output"]
1010 #[inline]
1011 pub fn opendr(self) -> &'a mut W {
1012 self.variant(IOMODEW::OPENDR)
1013 }
1014 #[doc = "Inverted input / ouput"]
1015 #[inline]
1016 pub fn inv(self) -> &'a mut W {
1017 self.variant(IOMODEW::INV)
1018 }
1019 #[doc = "Normal input / output"]
1020 #[inline]
1021 pub fn normal(self) -> &'a mut W {
1022 self.variant(IOMODEW::NORMAL)
1023 }
1024 #[doc = r" Writes raw bits to the field"]
1025 #[inline]
1026 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1027 const MASK: u8 = 7;
1028 const OFFSET: u8 = 24;
1029 self.w.bits &= !((MASK as u32) << OFFSET);
1030 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1031 self.w
1032 }
1033}
1034#[doc = r" Proxy"]
1035pub struct _RESERVED19W<'a> {
1036 w: &'a mut W,
1037}
1038impl<'a> _RESERVED19W<'a> {
1039 #[doc = r" Writes raw bits to the field"]
1040 #[inline]
1041 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1042 const MASK: u8 = 31;
1043 const OFFSET: u8 = 19;
1044 self.w.bits &= !((MASK as u32) << OFFSET);
1045 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1046 self.w
1047 }
1048}
1049#[doc = r" Proxy"]
1050pub struct _EDGE_IRQ_ENW<'a> {
1051 w: &'a mut W,
1052}
1053impl<'a> _EDGE_IRQ_ENW<'a> {
1054 #[doc = r" Sets the field bit"]
1055 pub fn set_bit(self) -> &'a mut W {
1056 self.bit(true)
1057 }
1058 #[doc = r" Clears the field bit"]
1059 pub fn clear_bit(self) -> &'a mut W {
1060 self.bit(false)
1061 }
1062 #[doc = r" Writes raw bits to the field"]
1063 #[inline]
1064 pub fn bit(self, value: bool) -> &'a mut W {
1065 const MASK: bool = true;
1066 const OFFSET: u8 = 18;
1067 self.w.bits &= !((MASK as u32) << OFFSET);
1068 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1069 self.w
1070 }
1071}
1072#[doc = "Values that can be written to the field `EDGE_DET`"]
1073#[derive(Clone, Copy, Debug, PartialEq)]
1074pub enum EDGE_DETW {
1075 #[doc = "Positive and negative edge detection"]
1076 BOTH,
1077 #[doc = "Positive edge detection"]
1078 POS,
1079 #[doc = "Negative edge detection"]
1080 NEG,
1081 #[doc = "No edge detection"]
1082 NONE,
1083}
1084impl EDGE_DETW {
1085 #[allow(missing_docs)]
1086 #[doc(hidden)]
1087 #[inline]
1088 pub fn _bits(&self) -> u8 {
1089 match *self {
1090 EDGE_DETW::BOTH => 3,
1091 EDGE_DETW::POS => 2,
1092 EDGE_DETW::NEG => 1,
1093 EDGE_DETW::NONE => 0,
1094 }
1095 }
1096}
1097#[doc = r" Proxy"]
1098pub struct _EDGE_DETW<'a> {
1099 w: &'a mut W,
1100}
1101impl<'a> _EDGE_DETW<'a> {
1102 #[doc = r" Writes `variant` to the field"]
1103 #[inline]
1104 pub fn variant(self, variant: EDGE_DETW) -> &'a mut W {
1105 {
1106 self.bits(variant._bits())
1107 }
1108 }
1109 #[doc = "Positive and negative edge detection"]
1110 #[inline]
1111 pub fn both(self) -> &'a mut W {
1112 self.variant(EDGE_DETW::BOTH)
1113 }
1114 #[doc = "Positive edge detection"]
1115 #[inline]
1116 pub fn pos(self) -> &'a mut W {
1117 self.variant(EDGE_DETW::POS)
1118 }
1119 #[doc = "Negative edge detection"]
1120 #[inline]
1121 pub fn neg(self) -> &'a mut W {
1122 self.variant(EDGE_DETW::NEG)
1123 }
1124 #[doc = "No edge detection"]
1125 #[inline]
1126 pub fn none(self) -> &'a mut W {
1127 self.variant(EDGE_DETW::NONE)
1128 }
1129 #[doc = r" Writes raw bits to the field"]
1130 #[inline]
1131 pub fn bits(self, value: u8) -> &'a mut W {
1132 const MASK: u8 = 3;
1133 const OFFSET: u8 = 16;
1134 self.w.bits &= !((MASK as u32) << OFFSET);
1135 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1136 self.w
1137 }
1138}
1139#[doc = "Values that can be written to the field `PULL_CTL`"]
1140#[derive(Clone, Copy, Debug, PartialEq)]
1141pub enum PULL_CTLW {
1142 #[doc = "No pull"]
1143 DIS,
1144 #[doc = "Pull up"]
1145 UP,
1146 #[doc = "Pull down"]
1147 DWN,
1148}
1149impl PULL_CTLW {
1150 #[allow(missing_docs)]
1151 #[doc(hidden)]
1152 #[inline]
1153 pub fn _bits(&self) -> u8 {
1154 match *self {
1155 PULL_CTLW::DIS => 3,
1156 PULL_CTLW::UP => 2,
1157 PULL_CTLW::DWN => 1,
1158 }
1159 }
1160}
1161#[doc = r" Proxy"]
1162pub struct _PULL_CTLW<'a> {
1163 w: &'a mut W,
1164}
1165impl<'a> _PULL_CTLW<'a> {
1166 #[doc = r" Writes `variant` to the field"]
1167 #[inline]
1168 pub fn variant(self, variant: PULL_CTLW) -> &'a mut W {
1169 unsafe { self.bits(variant._bits()) }
1170 }
1171 #[doc = "No pull"]
1172 #[inline]
1173 pub fn dis(self) -> &'a mut W {
1174 self.variant(PULL_CTLW::DIS)
1175 }
1176 #[doc = "Pull up"]
1177 #[inline]
1178 pub fn up(self) -> &'a mut W {
1179 self.variant(PULL_CTLW::UP)
1180 }
1181 #[doc = "Pull down"]
1182 #[inline]
1183 pub fn dwn(self) -> &'a mut W {
1184 self.variant(PULL_CTLW::DWN)
1185 }
1186 #[doc = r" Writes raw bits to the field"]
1187 #[inline]
1188 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1189 const MASK: u8 = 3;
1190 const OFFSET: u8 = 13;
1191 self.w.bits &= !((MASK as u32) << OFFSET);
1192 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1193 self.w
1194 }
1195}
1196#[doc = r" Proxy"]
1197pub struct _SLEW_REDW<'a> {
1198 w: &'a mut W,
1199}
1200impl<'a> _SLEW_REDW<'a> {
1201 #[doc = r" Sets the field bit"]
1202 pub fn set_bit(self) -> &'a mut W {
1203 self.bit(true)
1204 }
1205 #[doc = r" Clears the field bit"]
1206 pub fn clear_bit(self) -> &'a mut W {
1207 self.bit(false)
1208 }
1209 #[doc = r" Writes raw bits to the field"]
1210 #[inline]
1211 pub fn bit(self, value: bool) -> &'a mut W {
1212 const MASK: bool = true;
1213 const OFFSET: u8 = 12;
1214 self.w.bits &= !((MASK as u32) << OFFSET);
1215 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1216 self.w
1217 }
1218}
1219#[doc = "Values that can be written to the field `IOCURR`"]
1220#[derive(Clone, Copy, Debug, PartialEq)]
1221pub enum IOCURRW {
1222 #[doc = "Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO"]
1223 _4_8MA,
1224 #[doc = "High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO"]
1225 _4MA,
1226 #[doc = "Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO"]
1227 _2MA,
1228}
1229impl IOCURRW {
1230 #[allow(missing_docs)]
1231 #[doc(hidden)]
1232 #[inline]
1233 pub fn _bits(&self) -> u8 {
1234 match *self {
1235 IOCURRW::_4_8MA => 2,
1236 IOCURRW::_4MA => 1,
1237 IOCURRW::_2MA => 0,
1238 }
1239 }
1240}
1241#[doc = r" Proxy"]
1242pub struct _IOCURRW<'a> {
1243 w: &'a mut W,
1244}
1245impl<'a> _IOCURRW<'a> {
1246 #[doc = r" Writes `variant` to the field"]
1247 #[inline]
1248 pub fn variant(self, variant: IOCURRW) -> &'a mut W {
1249 unsafe { self.bits(variant._bits()) }
1250 }
1251 #[doc = "Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO"]
1252 #[inline]
1253 pub fn _4_8ma(self) -> &'a mut W {
1254 self.variant(IOCURRW::_4_8MA)
1255 }
1256 #[doc = "High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO"]
1257 #[inline]
1258 pub fn _4ma(self) -> &'a mut W {
1259 self.variant(IOCURRW::_4MA)
1260 }
1261 #[doc = "Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO"]
1262 #[inline]
1263 pub fn _2ma(self) -> &'a mut W {
1264 self.variant(IOCURRW::_2MA)
1265 }
1266 #[doc = r" Writes raw bits to the field"]
1267 #[inline]
1268 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1269 const MASK: u8 = 3;
1270 const OFFSET: u8 = 10;
1271 self.w.bits &= !((MASK as u32) << OFFSET);
1272 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1273 self.w
1274 }
1275}
1276#[doc = "Values that can be written to the field `IOSTR`"]
1277#[derive(Clone, Copy, Debug, PartialEq)]
1278pub enum IOSTRW {
1279 #[doc = "Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)"]
1280 MAX,
1281 #[doc = "Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)"]
1282 MED,
1283 #[doc = "Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)"]
1284 MIN,
1285 #[doc = "Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)"]
1286 AUTO,
1287}
1288impl IOSTRW {
1289 #[allow(missing_docs)]
1290 #[doc(hidden)]
1291 #[inline]
1292 pub fn _bits(&self) -> u8 {
1293 match *self {
1294 IOSTRW::MAX => 3,
1295 IOSTRW::MED => 2,
1296 IOSTRW::MIN => 1,
1297 IOSTRW::AUTO => 0,
1298 }
1299 }
1300}
1301#[doc = r" Proxy"]
1302pub struct _IOSTRW<'a> {
1303 w: &'a mut W,
1304}
1305impl<'a> _IOSTRW<'a> {
1306 #[doc = r" Writes `variant` to the field"]
1307 #[inline]
1308 pub fn variant(self, variant: IOSTRW) -> &'a mut W {
1309 {
1310 self.bits(variant._bits())
1311 }
1312 }
1313 #[doc = "Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)"]
1314 #[inline]
1315 pub fn max(self) -> &'a mut W {
1316 self.variant(IOSTRW::MAX)
1317 }
1318 #[doc = "Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)"]
1319 #[inline]
1320 pub fn med(self) -> &'a mut W {
1321 self.variant(IOSTRW::MED)
1322 }
1323 #[doc = "Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)"]
1324 #[inline]
1325 pub fn min(self) -> &'a mut W {
1326 self.variant(IOSTRW::MIN)
1327 }
1328 #[doc = "Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)"]
1329 #[inline]
1330 pub fn auto(self) -> &'a mut W {
1331 self.variant(IOSTRW::AUTO)
1332 }
1333 #[doc = r" Writes raw bits to the field"]
1334 #[inline]
1335 pub fn bits(self, value: u8) -> &'a mut W {
1336 const MASK: u8 = 3;
1337 const OFFSET: u8 = 8;
1338 self.w.bits &= !((MASK as u32) << OFFSET);
1339 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1340 self.w
1341 }
1342}
1343#[doc = "Values that can be written to the field `PORT_ID`"]
1344#[derive(Clone, Copy, Debug, PartialEq)]
1345pub enum PORT_IDW {
1346 #[doc = "RF Core SMI Command Link In"]
1347 RFC_SMI_CL_IN,
1348 #[doc = "RF Core SMI Command Link Out"]
1349 RFC_SMI_CL_OUT,
1350 #[doc = "RF Core SMI Data Link In"]
1351 RFC_SMI_DL_IN,
1352 #[doc = "RF Core SMI Data Link Out"]
1353 RFC_SMI_DL_OUT,
1354 #[doc = "RF Core Data In 1"]
1355 RFC_GPI1,
1356 #[doc = "RF Core Data In 0"]
1357 RFC_GPI0,
1358 #[doc = "RF Core Data Out 3"]
1359 RFC_GPO3,
1360 #[doc = "RF Core Data Out 2"]
1361 RFC_GPO2,
1362 #[doc = "RF Core Data Out 1"]
1363 RFC_GPO1,
1364 #[doc = "RF Core Data Out 0"]
1365 RFC_GPO0,
1366 #[doc = "RF Core Trace"]
1367 RFC_TRC,
1368 #[doc = "I2S MCLK "]
1369 I2S_MCLK,
1370 #[doc = "I2S BCLK "]
1371 I2S_BCLK,
1372 #[doc = "I2S WCLK "]
1373 I2S_WCLK,
1374 #[doc = "I2S Data 1"]
1375 I2S_AD1,
1376 #[doc = "I2S Data 0"]
1377 I2S_AD0,
1378 #[doc = "SSI1 CLK"]
1379 SSI1_CLK,
1380 #[doc = "SSI1 FSS "]
1381 SSI1_FSS,
1382 #[doc = "SSI1 TX "]
1383 SSI1_TX,
1384 #[doc = "SSI1 RX "]
1385 SSI1_RX,
1386 #[doc = "CPU SWV "]
1387 CPU_SWV,
1388 #[doc = "PORT EVENT 7\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1389 PORT_EVENT7,
1390 #[doc = "PORT EVENT 6\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1391 PORT_EVENT6,
1392 #[doc = "PORT EVENT 5\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1393 PORT_EVENT5,
1394 #[doc = "PORT EVENT 4\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1395 PORT_EVENT4,
1396 #[doc = "PORT EVENT 3\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1397 PORT_EVENT3,
1398 #[doc = "PORT EVENT 2\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1399 PORT_EVENT2,
1400 #[doc = "PORT EVENT 1\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1401 PORT_EVENT1,
1402 #[doc = "PORT EVENT 0\nCan be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1403 PORT_EVENT0,
1404 #[doc = "UART0 RTS "]
1405 UART0_RTS,
1406 #[doc = "UART0 CTS "]
1407 UART0_CTS,
1408 #[doc = "UART0 TX "]
1409 UART0_TX,
1410 #[doc = "UART0 RX "]
1411 UART0_RX,
1412 #[doc = "I2C Clock"]
1413 I2C_MSSCL,
1414 #[doc = "I2C Data"]
1415 I2C_MSSDA,
1416 #[doc = "SSI0 CLK"]
1417 SSI0_CLK,
1418 #[doc = "SSI0 FSS "]
1419 SSI0_FSS,
1420 #[doc = "SSI0 TX "]
1421 SSI0_TX,
1422 #[doc = "SSI0 RX "]
1423 SSI0_RX,
1424 #[doc = "AUX IO "]
1425 AUX_IO,
1426 #[doc = "AON 32 KHz clock (SCLK_LF)"]
1427 AON_CLK32K,
1428 #[doc = "General Purpose IO "]
1429 GPIO,
1430}
1431impl PORT_IDW {
1432 #[allow(missing_docs)]
1433 #[doc(hidden)]
1434 #[inline]
1435 pub fn _bits(&self) -> u8 {
1436 match *self {
1437 PORT_IDW::RFC_SMI_CL_IN => 56,
1438 PORT_IDW::RFC_SMI_CL_OUT => 55,
1439 PORT_IDW::RFC_SMI_DL_IN => 54,
1440 PORT_IDW::RFC_SMI_DL_OUT => 53,
1441 PORT_IDW::RFC_GPI1 => 52,
1442 PORT_IDW::RFC_GPI0 => 51,
1443 PORT_IDW::RFC_GPO3 => 50,
1444 PORT_IDW::RFC_GPO2 => 49,
1445 PORT_IDW::RFC_GPO1 => 48,
1446 PORT_IDW::RFC_GPO0 => 47,
1447 PORT_IDW::RFC_TRC => 46,
1448 PORT_IDW::I2S_MCLK => 41,
1449 PORT_IDW::I2S_BCLK => 40,
1450 PORT_IDW::I2S_WCLK => 39,
1451 PORT_IDW::I2S_AD1 => 38,
1452 PORT_IDW::I2S_AD0 => 37,
1453 PORT_IDW::SSI1_CLK => 36,
1454 PORT_IDW::SSI1_FSS => 35,
1455 PORT_IDW::SSI1_TX => 34,
1456 PORT_IDW::SSI1_RX => 33,
1457 PORT_IDW::CPU_SWV => 32,
1458 PORT_IDW::PORT_EVENT7 => 30,
1459 PORT_IDW::PORT_EVENT6 => 29,
1460 PORT_IDW::PORT_EVENT5 => 28,
1461 PORT_IDW::PORT_EVENT4 => 27,
1462 PORT_IDW::PORT_EVENT3 => 26,
1463 PORT_IDW::PORT_EVENT2 => 25,
1464 PORT_IDW::PORT_EVENT1 => 24,
1465 PORT_IDW::PORT_EVENT0 => 23,
1466 PORT_IDW::UART0_RTS => 18,
1467 PORT_IDW::UART0_CTS => 17,
1468 PORT_IDW::UART0_TX => 16,
1469 PORT_IDW::UART0_RX => 15,
1470 PORT_IDW::I2C_MSSCL => 14,
1471 PORT_IDW::I2C_MSSDA => 13,
1472 PORT_IDW::SSI0_CLK => 12,
1473 PORT_IDW::SSI0_FSS => 11,
1474 PORT_IDW::SSI0_TX => 10,
1475 PORT_IDW::SSI0_RX => 9,
1476 PORT_IDW::AUX_IO => 8,
1477 PORT_IDW::AON_CLK32K => 7,
1478 PORT_IDW::GPIO => 0,
1479 }
1480 }
1481}
1482#[doc = r" Proxy"]
1483pub struct _PORT_IDW<'a> {
1484 w: &'a mut W,
1485}
1486impl<'a> _PORT_IDW<'a> {
1487 #[doc = r" Writes `variant` to the field"]
1488 #[inline]
1489 pub fn variant(self, variant: PORT_IDW) -> &'a mut W {
1490 unsafe { self.bits(variant._bits()) }
1491 }
1492 #[doc = "RF Core SMI Command Link In"]
1493 #[inline]
1494 pub fn rfc_smi_cl_in(self) -> &'a mut W {
1495 self.variant(PORT_IDW::RFC_SMI_CL_IN)
1496 }
1497 #[doc = "RF Core SMI Command Link Out"]
1498 #[inline]
1499 pub fn rfc_smi_cl_out(self) -> &'a mut W {
1500 self.variant(PORT_IDW::RFC_SMI_CL_OUT)
1501 }
1502 #[doc = "RF Core SMI Data Link In"]
1503 #[inline]
1504 pub fn rfc_smi_dl_in(self) -> &'a mut W {
1505 self.variant(PORT_IDW::RFC_SMI_DL_IN)
1506 }
1507 #[doc = "RF Core SMI Data Link Out"]
1508 #[inline]
1509 pub fn rfc_smi_dl_out(self) -> &'a mut W {
1510 self.variant(PORT_IDW::RFC_SMI_DL_OUT)
1511 }
1512 #[doc = "RF Core Data In 1"]
1513 #[inline]
1514 pub fn rfc_gpi1(self) -> &'a mut W {
1515 self.variant(PORT_IDW::RFC_GPI1)
1516 }
1517 #[doc = "RF Core Data In 0"]
1518 #[inline]
1519 pub fn rfc_gpi0(self) -> &'a mut W {
1520 self.variant(PORT_IDW::RFC_GPI0)
1521 }
1522 #[doc = "RF Core Data Out 3"]
1523 #[inline]
1524 pub fn rfc_gpo3(self) -> &'a mut W {
1525 self.variant(PORT_IDW::RFC_GPO3)
1526 }
1527 #[doc = "RF Core Data Out 2"]
1528 #[inline]
1529 pub fn rfc_gpo2(self) -> &'a mut W {
1530 self.variant(PORT_IDW::RFC_GPO2)
1531 }
1532 #[doc = "RF Core Data Out 1"]
1533 #[inline]
1534 pub fn rfc_gpo1(self) -> &'a mut W {
1535 self.variant(PORT_IDW::RFC_GPO1)
1536 }
1537 #[doc = "RF Core Data Out 0"]
1538 #[inline]
1539 pub fn rfc_gpo0(self) -> &'a mut W {
1540 self.variant(PORT_IDW::RFC_GPO0)
1541 }
1542 #[doc = "RF Core Trace"]
1543 #[inline]
1544 pub fn rfc_trc(self) -> &'a mut W {
1545 self.variant(PORT_IDW::RFC_TRC)
1546 }
1547 #[doc = "I2S MCLK"]
1548 #[inline]
1549 pub fn i2s_mclk(self) -> &'a mut W {
1550 self.variant(PORT_IDW::I2S_MCLK)
1551 }
1552 #[doc = "I2S BCLK"]
1553 #[inline]
1554 pub fn i2s_bclk(self) -> &'a mut W {
1555 self.variant(PORT_IDW::I2S_BCLK)
1556 }
1557 #[doc = "I2S WCLK"]
1558 #[inline]
1559 pub fn i2s_wclk(self) -> &'a mut W {
1560 self.variant(PORT_IDW::I2S_WCLK)
1561 }
1562 #[doc = "I2S Data 1"]
1563 #[inline]
1564 pub fn i2s_ad1(self) -> &'a mut W {
1565 self.variant(PORT_IDW::I2S_AD1)
1566 }
1567 #[doc = "I2S Data 0"]
1568 #[inline]
1569 pub fn i2s_ad0(self) -> &'a mut W {
1570 self.variant(PORT_IDW::I2S_AD0)
1571 }
1572 #[doc = "SSI1 CLK"]
1573 #[inline]
1574 pub fn ssi1_clk(self) -> &'a mut W {
1575 self.variant(PORT_IDW::SSI1_CLK)
1576 }
1577 #[doc = "SSI1 FSS"]
1578 #[inline]
1579 pub fn ssi1_fss(self) -> &'a mut W {
1580 self.variant(PORT_IDW::SSI1_FSS)
1581 }
1582 #[doc = "SSI1 TX"]
1583 #[inline]
1584 pub fn ssi1_tx(self) -> &'a mut W {
1585 self.variant(PORT_IDW::SSI1_TX)
1586 }
1587 #[doc = "SSI1 RX"]
1588 #[inline]
1589 pub fn ssi1_rx(self) -> &'a mut W {
1590 self.variant(PORT_IDW::SSI1_RX)
1591 }
1592 #[doc = "CPU SWV"]
1593 #[inline]
1594 pub fn cpu_swv(self) -> &'a mut W {
1595 self.variant(PORT_IDW::CPU_SWV)
1596 }
1597 #[doc = "PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1598 #[inline]
1599 pub fn port_event7(self) -> &'a mut W {
1600 self.variant(PORT_IDW::PORT_EVENT7)
1601 }
1602 #[doc = "PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1603 #[inline]
1604 pub fn port_event6(self) -> &'a mut W {
1605 self.variant(PORT_IDW::PORT_EVENT6)
1606 }
1607 #[doc = "PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1608 #[inline]
1609 pub fn port_event5(self) -> &'a mut W {
1610 self.variant(PORT_IDW::PORT_EVENT5)
1611 }
1612 #[doc = "PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1613 #[inline]
1614 pub fn port_event4(self) -> &'a mut W {
1615 self.variant(PORT_IDW::PORT_EVENT4)
1616 }
1617 #[doc = "PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1618 #[inline]
1619 pub fn port_event3(self) -> &'a mut W {
1620 self.variant(PORT_IDW::PORT_EVENT3)
1621 }
1622 #[doc = "PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1623 #[inline]
1624 pub fn port_event2(self) -> &'a mut W {
1625 self.variant(PORT_IDW::PORT_EVENT2)
1626 }
1627 #[doc = "PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1628 #[inline]
1629 pub fn port_event1(self) -> &'a mut W {
1630 self.variant(PORT_IDW::PORT_EVENT1)
1631 }
1632 #[doc = "PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc"]
1633 #[inline]
1634 pub fn port_event0(self) -> &'a mut W {
1635 self.variant(PORT_IDW::PORT_EVENT0)
1636 }
1637 #[doc = "UART0 RTS"]
1638 #[inline]
1639 pub fn uart0_rts(self) -> &'a mut W {
1640 self.variant(PORT_IDW::UART0_RTS)
1641 }
1642 #[doc = "UART0 CTS"]
1643 #[inline]
1644 pub fn uart0_cts(self) -> &'a mut W {
1645 self.variant(PORT_IDW::UART0_CTS)
1646 }
1647 #[doc = "UART0 TX"]
1648 #[inline]
1649 pub fn uart0_tx(self) -> &'a mut W {
1650 self.variant(PORT_IDW::UART0_TX)
1651 }
1652 #[doc = "UART0 RX"]
1653 #[inline]
1654 pub fn uart0_rx(self) -> &'a mut W {
1655 self.variant(PORT_IDW::UART0_RX)
1656 }
1657 #[doc = "I2C Clock"]
1658 #[inline]
1659 pub fn i2c_msscl(self) -> &'a mut W {
1660 self.variant(PORT_IDW::I2C_MSSCL)
1661 }
1662 #[doc = "I2C Data"]
1663 #[inline]
1664 pub fn i2c_mssda(self) -> &'a mut W {
1665 self.variant(PORT_IDW::I2C_MSSDA)
1666 }
1667 #[doc = "SSI0 CLK"]
1668 #[inline]
1669 pub fn ssi0_clk(self) -> &'a mut W {
1670 self.variant(PORT_IDW::SSI0_CLK)
1671 }
1672 #[doc = "SSI0 FSS"]
1673 #[inline]
1674 pub fn ssi0_fss(self) -> &'a mut W {
1675 self.variant(PORT_IDW::SSI0_FSS)
1676 }
1677 #[doc = "SSI0 TX"]
1678 #[inline]
1679 pub fn ssi0_tx(self) -> &'a mut W {
1680 self.variant(PORT_IDW::SSI0_TX)
1681 }
1682 #[doc = "SSI0 RX"]
1683 #[inline]
1684 pub fn ssi0_rx(self) -> &'a mut W {
1685 self.variant(PORT_IDW::SSI0_RX)
1686 }
1687 #[doc = "AUX IO"]
1688 #[inline]
1689 pub fn aux_io(self) -> &'a mut W {
1690 self.variant(PORT_IDW::AUX_IO)
1691 }
1692 #[doc = "AON 32 KHz clock (SCLK_LF)"]
1693 #[inline]
1694 pub fn aon_clk32k(self) -> &'a mut W {
1695 self.variant(PORT_IDW::AON_CLK32K)
1696 }
1697 #[doc = "General Purpose IO"]
1698 #[inline]
1699 pub fn gpio(self) -> &'a mut W {
1700 self.variant(PORT_IDW::GPIO)
1701 }
1702 #[doc = r" Writes raw bits to the field"]
1703 #[inline]
1704 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1705 const MASK: u8 = 63;
1706 const OFFSET: u8 = 0;
1707 self.w.bits &= !((MASK as u32) << OFFSET);
1708 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1709 self.w
1710 }
1711}
1712impl R {
1713 #[doc = r" Value of the register as raw bits"]
1714 #[inline]
1715 pub fn bits(&self) -> u32 {
1716 self.bits
1717 }
1718 #[doc = "Bit 31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
1719 #[inline]
1720 pub fn reserved31(&self) -> RESERVED31R {
1721 let bits = {
1722 const MASK: bool = true;
1723 const OFFSET: u8 = 31;
1724 ((self.bits >> OFFSET) & MASK as u32) != 0
1725 };
1726 RESERVED31R { bits }
1727 }
1728 #[doc = "Bit 30 - 0: Input hysteresis disable 1: Input hysteresis enable"]
1729 #[inline]
1730 pub fn hyst_en(&self) -> HYST_ENR {
1731 let bits = {
1732 const MASK: bool = true;
1733 const OFFSET: u8 = 30;
1734 ((self.bits >> OFFSET) & MASK as u32) != 0
1735 };
1736 HYST_ENR { bits }
1737 }
1738 #[doc = "Bit 29 - 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored."]
1739 #[inline]
1740 pub fn ie(&self) -> IER {
1741 let bits = {
1742 const MASK: bool = true;
1743 const OFFSET: u8 = 29;
1744 ((self.bits >> OFFSET) & MASK as u32) != 0
1745 };
1746 IER { bits }
1747 }
1748 #[doc = "Bits 27:28 - If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO."]
1749 #[inline]
1750 pub fn wu_cfg(&self) -> WU_CFGR {
1751 let bits = {
1752 const MASK: u8 = 3;
1753 const OFFSET: u8 = 27;
1754 ((self.bits >> OFFSET) & MASK as u32) as u8
1755 };
1756 WU_CFGR { bits }
1757 }
1758 #[doc = "Bits 24:26 - IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior."]
1759 #[inline]
1760 pub fn iomode(&self) -> IOMODER {
1761 IOMODER::_from({
1762 const MASK: u8 = 7;
1763 const OFFSET: u8 = 24;
1764 ((self.bits >> OFFSET) & MASK as u32) as u8
1765 })
1766 }
1767 #[doc = "Bits 19:23 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
1768 #[inline]
1769 pub fn reserved19(&self) -> RESERVED19R {
1770 let bits = {
1771 const MASK: u8 = 31;
1772 const OFFSET: u8 = 19;
1773 ((self.bits >> OFFSET) & MASK as u32) as u8
1774 };
1775 RESERVED19R { bits }
1776 }
1777 #[doc = "Bit 18 - 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)"]
1778 #[inline]
1779 pub fn edge_irq_en(&self) -> EDGE_IRQ_ENR {
1780 let bits = {
1781 const MASK: bool = true;
1782 const OFFSET: u8 = 18;
1783 ((self.bits >> OFFSET) & MASK as u32) != 0
1784 };
1785 EDGE_IRQ_ENR { bits }
1786 }
1787 #[doc = "Bits 16:17 - Enable generation of edge detection events on this IO"]
1788 #[inline]
1789 pub fn edge_det(&self) -> EDGE_DETR {
1790 EDGE_DETR::_from({
1791 const MASK: u8 = 3;
1792 const OFFSET: u8 = 16;
1793 ((self.bits >> OFFSET) & MASK as u32) as u8
1794 })
1795 }
1796 #[doc = "Bit 15 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
1797 #[inline]
1798 pub fn reserved15(&self) -> RESERVED15R {
1799 let bits = {
1800 const MASK: bool = true;
1801 const OFFSET: u8 = 15;
1802 ((self.bits >> OFFSET) & MASK as u32) != 0
1803 };
1804 RESERVED15R { bits }
1805 }
1806 #[doc = "Bits 13:14 - Pull control"]
1807 #[inline]
1808 pub fn pull_ctl(&self) -> PULL_CTLR {
1809 PULL_CTLR::_from({
1810 const MASK: u8 = 3;
1811 const OFFSET: u8 = 13;
1812 ((self.bits >> OFFSET) & MASK as u32) as u8
1813 })
1814 }
1815 #[doc = "Bit 12 - 0: Normal slew rate 1: Enables reduced slew rate in output driver."]
1816 #[inline]
1817 pub fn slew_red(&self) -> SLEW_REDR {
1818 let bits = {
1819 const MASK: bool = true;
1820 const OFFSET: u8 = 12;
1821 ((self.bits >> OFFSET) & MASK as u32) != 0
1822 };
1823 SLEW_REDR { bits }
1824 }
1825 #[doc = "Bits 10:11 - Selects IO current mode of this IO."]
1826 #[inline]
1827 pub fn iocurr(&self) -> IOCURRR {
1828 IOCURRR::_from({
1829 const MASK: u8 = 3;
1830 const OFFSET: u8 = 10;
1831 ((self.bits >> OFFSET) & MASK as u32) as u8
1832 })
1833 }
1834 #[doc = "Bits 8:9 - Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR"]
1835 #[inline]
1836 pub fn iostr(&self) -> IOSTRR {
1837 IOSTRR::_from({
1838 const MASK: u8 = 3;
1839 const OFFSET: u8 = 8;
1840 ((self.bits >> OFFSET) & MASK as u32) as u8
1841 })
1842 }
1843 #[doc = "Bits 6:7 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
1844 #[inline]
1845 pub fn reserved6(&self) -> RESERVED6R {
1846 let bits = {
1847 const MASK: u8 = 3;
1848 const OFFSET: u8 = 6;
1849 ((self.bits >> OFFSET) & MASK as u32) as u8
1850 };
1851 RESERVED6R { bits }
1852 }
1853 #[doc = "Bits 0:5 - Selects usage for DIO21"]
1854 #[inline]
1855 pub fn port_id(&self) -> PORT_IDR {
1856 PORT_IDR::_from({
1857 const MASK: u8 = 63;
1858 const OFFSET: u8 = 0;
1859 ((self.bits >> OFFSET) & MASK as u32) as u8
1860 })
1861 }
1862}
1863impl W {
1864 #[doc = r" Reset value of the register"]
1865 #[inline]
1866 pub fn reset_value() -> W {
1867 W { bits: 0 }
1868 }
1869 #[doc = r" Writes raw bits to the register"]
1870 #[inline]
1871 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1872 self.bits = bits;
1873 self
1874 }
1875 #[doc = "Bit 30 - 0: Input hysteresis disable 1: Input hysteresis enable"]
1876 #[inline]
1877 pub fn hyst_en(&mut self) -> _HYST_ENW {
1878 _HYST_ENW { w: self }
1879 }
1880 #[doc = "Bit 29 - 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored."]
1881 #[inline]
1882 pub fn ie(&mut self) -> _IEW {
1883 _IEW { w: self }
1884 }
1885 #[doc = "Bits 27:28 - If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO."]
1886 #[inline]
1887 pub fn wu_cfg(&mut self) -> _WU_CFGW {
1888 _WU_CFGW { w: self }
1889 }
1890 #[doc = "Bits 24:26 - IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior."]
1891 #[inline]
1892 pub fn iomode(&mut self) -> _IOMODEW {
1893 _IOMODEW { w: self }
1894 }
1895 #[doc = "Bits 19:23 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
1896 #[inline]
1897 pub fn reserved19(&mut self) -> _RESERVED19W {
1898 _RESERVED19W { w: self }
1899 }
1900 #[doc = "Bit 18 - 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)"]
1901 #[inline]
1902 pub fn edge_irq_en(&mut self) -> _EDGE_IRQ_ENW {
1903 _EDGE_IRQ_ENW { w: self }
1904 }
1905 #[doc = "Bits 16:17 - Enable generation of edge detection events on this IO"]
1906 #[inline]
1907 pub fn edge_det(&mut self) -> _EDGE_DETW {
1908 _EDGE_DETW { w: self }
1909 }
1910 #[doc = "Bits 13:14 - Pull control"]
1911 #[inline]
1912 pub fn pull_ctl(&mut self) -> _PULL_CTLW {
1913 _PULL_CTLW { w: self }
1914 }
1915 #[doc = "Bit 12 - 0: Normal slew rate 1: Enables reduced slew rate in output driver."]
1916 #[inline]
1917 pub fn slew_red(&mut self) -> _SLEW_REDW {
1918 _SLEW_REDW { w: self }
1919 }
1920 #[doc = "Bits 10:11 - Selects IO current mode of this IO."]
1921 #[inline]
1922 pub fn iocurr(&mut self) -> _IOCURRW {
1923 _IOCURRW { w: self }
1924 }
1925 #[doc = "Bits 8:9 - Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR"]
1926 #[inline]
1927 pub fn iostr(&mut self) -> _IOSTRW {
1928 _IOSTRW { w: self }
1929 }
1930 #[doc = "Bits 0:5 - Selects usage for DIO21"]
1931 #[inline]
1932 pub fn port_id(&mut self) -> _PORT_IDW {
1933 _PORT_IDW { w: self }
1934 }
1935}