cc2650/cpu_dwt/
mask1.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::MASK1 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R { bits: self.register.get() }
26    }
27    #[doc = r" Writes to the register"]
28    #[inline]
29    pub fn write<F>(&self, f: F)
30    where
31        F: FnOnce(&mut W) -> &mut W,
32    {
33        let mut w = W::reset_value();
34        f(&mut w);
35        self.register.set(w.bits);
36    }
37    #[doc = r" Writes the reset value to the register"]
38    #[inline]
39    pub fn reset(&self) {
40        self.write(|w| w)
41    }
42}
43#[doc = r" Value of the field"]
44pub struct RESERVED4R {
45    bits: u32,
46}
47impl RESERVED4R {
48    #[doc = r" Value of the field as raw bits"]
49    #[inline]
50    pub fn bits(&self) -> u32 {
51        self.bits
52    }
53}
54#[doc = r" Value of the field"]
55pub struct MASKR {
56    bits: u8,
57}
58impl MASKR {
59    #[doc = r" Value of the field as raw bits"]
60    #[inline]
61    pub fn bits(&self) -> u8 {
62        self.bits
63    }
64}
65#[doc = r" Proxy"]
66pub struct _RESERVED4W<'a> {
67    w: &'a mut W,
68}
69impl<'a> _RESERVED4W<'a> {
70    #[doc = r" Writes raw bits to the field"]
71    #[inline]
72    pub unsafe fn bits(self, value: u32) -> &'a mut W {
73        const MASK: u32 = 268435455;
74        const OFFSET: u8 = 4;
75        self.w.bits &= !((MASK as u32) << OFFSET);
76        self.w.bits |= ((value & MASK) as u32) << OFFSET;
77        self.w
78    }
79}
80#[doc = r" Proxy"]
81pub struct _MASKW<'a> {
82    w: &'a mut W,
83}
84impl<'a> _MASKW<'a> {
85    #[doc = r" Writes raw bits to the field"]
86    #[inline]
87    pub unsafe fn bits(self, value: u8) -> &'a mut W {
88        const MASK: u8 = 15;
89        const OFFSET: u8 = 0;
90        self.w.bits &= !((MASK as u32) << OFFSET);
91        self.w.bits |= ((value & MASK) as u32) << OFFSET;
92        self.w
93    }
94}
95impl R {
96    #[doc = r" Value of the register as raw bits"]
97    #[inline]
98    pub fn bits(&self) -> u32 {
99        self.bits
100    }
101    #[doc = "Bits 4:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
102    #[inline]
103    pub fn reserved4(&self) -> RESERVED4R {
104        let bits = {
105            const MASK: u32 = 268435455;
106            const OFFSET: u8 = 4;
107            ((self.bits >> OFFSET) & MASK as u32) as u32
108        };
109        RESERVED4R { bits }
110    }
111    #[doc = "Bits 0:3 - Mask on data address when matching against COMP1. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP1. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word."]
112    #[inline]
113    pub fn mask(&self) -> MASKR {
114        let bits = {
115            const MASK: u8 = 15;
116            const OFFSET: u8 = 0;
117            ((self.bits >> OFFSET) & MASK as u32) as u8
118        };
119        MASKR { bits }
120    }
121}
122impl W {
123    #[doc = r" Reset value of the register"]
124    #[inline]
125    pub fn reset_value() -> W {
126        W { bits: 0 }
127    }
128    #[doc = r" Writes raw bits to the register"]
129    #[inline]
130    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
131        self.bits = bits;
132        self
133    }
134    #[doc = "Bits 4:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
135    #[inline]
136    pub fn reserved4(&mut self) -> _RESERVED4W {
137        _RESERVED4W { w: self }
138    }
139    #[doc = "Bits 0:3 - Mask on data address when matching against COMP1. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP1. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word."]
140    #[inline]
141    pub fn mask(&mut self) -> _MASKW {
142        _MASKW { w: self }
143    }
144}
cc2650/cpu_dwt/mask1.rs

cc2650/cpu_dwt/
mask1.rs
