[−][src]Struct cc2650::ssi0::cpsr::R
Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn cpsdvsr(&self) -> CPSDVSRR[src]
Bits 0:7 - Clock prescale divisor: This field specifies the division factor by which the input system clock to SSI must be internally divided before further use. The value programmed into this field must be an even non-zero number (2-254). The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.
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