Struct cc2650::cpu_dwt::ctrl::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved26(&mut self) -> _RESERVED26W

Bits 26:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn nocyccnt(&mut self) -> _NOCYCCNTW

Bit 25 - When set, CYCCNT is not supported.

pub fn noprfcnt(&mut self) -> _NOPRFCNTW

Bit 24 - When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported.

pub fn reserved23(&mut self) -> _RESERVED23W

Bit 23 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn cycevtena(&mut self) -> _CYCEVTENAW

Bit 22 - Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. This event is only emitted if PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. 0: Cycle count events disabled 1: Cycle count events enabled

pub fn foldevtena(&mut self) -> _FOLDEVTENAW

Bit 21 - Enables Folded instruction count event. Emits an event when FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. 0: Folded instruction count events disabled. 1: Folded instruction count events enabled.

pub fn lsuevtena(&mut self) -> _LSUEVTENAW

Bit 20 - Enables LSU count event. Emits an event when LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. 0: LSU count events disabled. 1: LSU count events enabled.

pub fn sleepevtena(&mut self) -> _SLEEPEVTENAW

Bit 19 - Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 cycles that the processor is sleeping). 0: Sleep count events disabled. 1: Sleep count events enabled.

pub fn excevtena(&mut self) -> _EXCEVTENAW

Bit 18 - Enables Interrupt overhead event. Emits an event when EXCCNT overflows (every 256 cycles of interrupt overhead). 0x0: Interrupt overhead event disabled. 0x1: Interrupt overhead event enabled.

pub fn cpievtena(&mut self) -> _CPIEVTENAW

Bit 17 - Enables CPI count event. Emits an event when CPICNT overflows (every 256 cycles of multi-cycle instructions). 0: CPI counter events disabled. 1: CPI counter events enabled.

pub fn exctrcena(&mut self) -> _EXCTRCENAW

Bit 16 - Enables Interrupt event tracing. 0: Interrupt event trace disabled. 1: Interrupt event trace enabled.

pub fn reserved13(&mut self) -> _RESERVED13W

Bits 13:15 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn pcsampleena(&mut self) -> _PCSAMPLEENAW

Bit 12 - Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling event disabled. 1: Sampling event enabled.

pub fn synctap(&mut self) -> _SYNCTAPW

Bits 10:11 - Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA must also be enabled for this feature. Synchronization packets (if enabled) are generated on tap transitions (0 to1 or 1 to 0).

pub fn cyctap(&mut self) -> _CYCTAPW

Bit 9 - Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or cycle count event (see details in CYCEVTENA).

pub fn postcnt(&mut self) -> _POSTCNTW

Bits 5:8 - Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the value from POSTPRESET.

pub fn postpreset(&mut self) -> _POSTPRESETW

Bits 1:4 - Reload value for post-scalar counter POSTCNT. When 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, it forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change.

pub fn cyccntena(&mut self) -> _CYCCNTENAW

Bit 0 - Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes.