Struct cc2650::aon_rtc::ctl::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn comb_ev_mask(&mut self) -> _COMB_EV_MASKW

Bits 16:18 - Eventmask selecting which delayed events that form the combined event.

pub fn ev_delay(&mut self) -> _EV_DELAYW

Bits 8:11 - Number of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed

pub fn reset(&mut self) -> _RESETW

Bit 7 - RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when reset takes effect

pub fn rtc_4khz_en(&mut self) -> _RTC_4KHZ_ENW

Bit 2 - RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN)

pub fn rtc_upd_en(&mut self) -> _RTC_UPD_ENW

Bit 1 - RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2 0: RTC_UPD signal is forced to 0 1: RTC_UPD signal is toggling @16 kHz

pub fn en(&mut self) -> _ENW

Bit 0 - Enable RTC counter 0: Halted (frozen) 1: Running