cc2538/sys_ctrl/
scgcssi.rs

1#[doc = "Reader of register SCGCSSI"]
2pub type R = crate::R<u32, super::SCGCSSI>;
3#[doc = "Writer for register SCGCSSI"]
4pub type W = crate::W<u32, super::SCGCSSI>;
5#[doc = "Register SCGCSSI `reset()`'s with value 0"]
6impl crate::ResetValue for super::SCGCSSI {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | (((value as u32) & 0x3fff_ffff) << 2);
24        self.w
25    }
26}
27#[doc = "Reader of field `SSI1`"]
28pub type SSI1_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `SSI1`"]
30pub struct SSI1_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> SSI1_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
48        self.w
49    }
50}
51#[doc = "Reader of field `SSI0`"]
52pub type SSI0_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `SSI0`"]
54pub struct SSI0_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> SSI0_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W {
61        self.bit(true)
62    }
63    #[doc = r"Clears the field bit"]
64    #[inline(always)]
65    pub fn clear_bit(self) -> &'a mut W {
66        self.bit(false)
67    }
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub fn bit(self, value: bool) -> &'a mut W {
71        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
72        self.w
73    }
74}
75impl R {
76    #[doc = "Bits 2:31 - 31:2\\] This register is 8 bits in a 32-bit address space."]
77    #[inline(always)]
78    pub fn reserved32(&self) -> RESERVED32_R {
79        RESERVED32_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32)
80    }
81    #[doc = "Bit 1 - 1:1\\] 0: Clock for SSI1 is gated. 1: Clock for SSI1 is enabled."]
82    #[inline(always)]
83    pub fn ssi1(&self) -> SSI1_R {
84        SSI1_R::new(((self.bits >> 1) & 0x01) != 0)
85    }
86    #[doc = "Bit 0 - 0:0\\] 0: Clock for SSI0 is gated. 1: Clock for SSI0 is enabled."]
87    #[inline(always)]
88    pub fn ssi0(&self) -> SSI0_R {
89        SSI0_R::new((self.bits & 0x01) != 0)
90    }
91}
92impl W {
93    #[doc = "Bits 2:31 - 31:2\\] This register is 8 bits in a 32-bit address space."]
94    #[inline(always)]
95    pub fn reserved32(&mut self) -> RESERVED32_W {
96        RESERVED32_W { w: self }
97    }
98    #[doc = "Bit 1 - 1:1\\] 0: Clock for SSI1 is gated. 1: Clock for SSI1 is enabled."]
99    #[inline(always)]
100    pub fn ssi1(&mut self) -> SSI1_W {
101        SSI1_W { w: self }
102    }
103    #[doc = "Bit 0 - 0:0\\] 0: Clock for SSI0 is gated. 1: Clock for SSI0 is enabled."]
104    #[inline(always)]
105    pub fn ssi0(&mut self) -> SSI0_W {
106        SSI0_W { w: self }
107    }
108}
cc2538/sys_ctrl/scgcssi.rs

cc2538/sys_ctrl/
scgcssi.rs
