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#[doc = "Reader of register CTRL"] pub type R = crate::R<u32, super::CTRL>; #[doc = "Writer for register CTRL"] pub type W = crate::W<u32, super::CTRL>; #[doc = "Register CTRL `reset()`'s with value 0"] impl crate::ResetValue for super::CTRL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `Reserved28`"] pub type RESERVED28_R = crate::R<u32, u32>; #[doc = "Write proxy for field `Reserved28`"] pub struct RESERVED28_W<'a> { w: &'a mut W, } impl<'a> RESERVED28_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u32) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0fff_ffff << 4)) | (((value as u32) & 0x0fff_ffff) << 4); self.w } } #[doc = "Reader of field `ACK`"] pub type ACK_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ACK`"] pub struct ACK_W<'a> { w: &'a mut W, } impl<'a> ACK_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `STOP`"] pub type STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `STOP`"] pub struct STOP_W<'a> { w: &'a mut W, } impl<'a> STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `START`"] pub type START_R = crate::R<bool, bool>; #[doc = "Write proxy for field `START`"] pub struct START_W<'a> { w: &'a mut W, } impl<'a> START_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `RUN`"] pub type RUN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RUN`"] pub struct RUN_W<'a> { w: &'a mut W, } impl<'a> RUN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } impl R { #[doc = "Bits 4:31 - 31:4\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."] #[inline(always)] pub fn reserved28(&self) -> RESERVED28_R { RESERVED28_R::new(((self.bits >> 4) & 0x0fff_ffff) as u32) } #[doc = "Bit 3 - 3:3\\] Data acknowledge enable 0: The received data byte is not acknowledged automatically by the master. 1: The received data byte is acknowledged automatically by the master."] #[inline(always)] pub fn ack(&self) -> ACK_R { ACK_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 2 - 2:2\\] Generate STOP 0: The controller does not generate the STOP condition. 1: The controller generates the STOP condition."] #[inline(always)] pub fn stop(&self) -> STOP_R { STOP_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 1 - 1:1\\] Generate START 0: The controller does not generate the START condition. 1: The controller generates the START condition."] #[inline(always)] pub fn start(&self) -> START_R { START_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 0 - 0:0\\] I2C master enable 0: The master is disabled. 1: The master is enabled to transmit or receive data. When the BUSY bit is set, the other status bits are not valid."] #[inline(always)] pub fn run(&self) -> RUN_R { RUN_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bits 4:31 - 31:4\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."] #[inline(always)] pub fn reserved28(&mut self) -> RESERVED28_W { RESERVED28_W { w: self } } #[doc = "Bit 3 - 3:3\\] Data acknowledge enable 0: The received data byte is not acknowledged automatically by the master. 1: The received data byte is acknowledged automatically by the master."] #[inline(always)] pub fn ack(&mut self) -> ACK_W { ACK_W { w: self } } #[doc = "Bit 2 - 2:2\\] Generate STOP 0: The controller does not generate the STOP condition. 1: The controller generates the STOP condition."] #[inline(always)] pub fn stop(&mut self) -> STOP_W { STOP_W { w: self } } #[doc = "Bit 1 - 1:1\\] Generate START 0: The controller does not generate the START condition. 1: The controller generates the START condition."] #[inline(always)] pub fn start(&mut self) -> START_W { START_W { w: self } } #[doc = "Bit 0 - 0:0\\] I2C master enable 0: The master is disabled. 1: The master is enabled to transmit or receive data. When the BUSY bit is set, the other status bits are not valid."] #[inline(always)] pub fn run(&mut self) -> RUN_W { RUN_W { w: self } } }