Type Definition cc2538::aes::ctrl_int_stat::W

type W = W<u32, CTRL_INT_STAT>;

Writer for register CTRL_INT_STAT

Methods

impl W

pub fn dma_bus_err(&mut self) -> DMA_BUS_ERR_W

Bit 31 - 31:31] This bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared through the CTRL_INT_CLR register. Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation.

pub fn key_st_wr_err(&mut self) -> KEY_ST_WR_ERR_W

Bit 30 - 30:30] This bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared through the CTRL_INT_CLR register. Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected.

pub fn key_st_rd_err(&mut self) -> KEY_ST_RD_ERR_W

Bit 29 - 29:29] This bit is set when a read error is detected during the read of a key from the key store, while copying it to the AES core. The value of this register is held until it is cleared through the CTRL_INT_CLR register. Note: This error is asserted if a key location is selected in the key store that is not available.

pub fn reserved27(&mut self) -> RESERVED27_W

Bits 2:28 - 28:2] Bits should be ignored

pub fn dma_in_done(&mut self) -> DMA_IN_DONE_W

Bit 1 - 1:1] This read only bit returns the actual DMA data in done (irq_data_in_done) interrupt status of the DMA data in done interrupt output pin (irq_data_in_done).

pub fn result_av(&mut self) -> RESULT_AV_W

Bit 0 - 0:0] This read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av).