Type Definition cc2538::aes::aes_ctrl::R

type R = R<u32, AES_CTRL>;

Reader of register AES_CTRL

Methods

impl R

pub fn context_ready(&self) -> CONTEXT_READY_R

Bit 31 - 31:31] If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context.

pub fn saved_context_ready(&self) -> SAVED_CONTEXT_READY_R

Bit 30 - 30:30] If 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve. This bit is only asserted if the save_context bit is set to 1. The bit is mutual exclusive with the context_ready bit. Writing one clears the bit to 0, indicating the AES core can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read. Note: All other mode bit writes are ignored when this mode bit is written with 1. Note: This bit is controlled automatically by the EIP-120t for TAG read DMA operations.

pub fn save_context(&self) -> SAVE_CONTEXT_R

Bit 29 - 29:29] This bit indicates that an authentication TAG or result IV needs to be stored as a result context. Typically this bit must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV. If this bit is set, the engine retains its full context until the TAG and/or IV registers are read. The TAG or IV must be read before the AES engine can start a new operation.

pub fn reserved1(&self) -> RESERVED1_R

Bits 25:28 - 28:25] Bits should be written with a value of 0. and ignored on a read.

pub fn ccm_m(&self) -> CCM_M_R

Bits 22:24 - 24:22] Defines M, which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-120t always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.

pub fn ccm_l(&self) -> CCM_L_R

Bits 19:21 - 21:19] Defines L, which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported.

pub fn ccm(&self) -> CCM_R

Bit 18 - 18:18] If set to 1, AES-CCM is selected AES-CCM is a combined mode, using AES for authentication and encryption. Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR; selecting other AES modes than CTR mode is invalid.

pub fn gcm(&self) -> GCM_R

Bits 16:17 - 17:16] Set these bits to 11 to select AES-GCM mode. AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR Bit combination description: 00 = No GCM mode 01 = Reserved, do not select 10 = Reserved, do not select 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), other GCM modes are not allowed.

pub fn cbc_mac(&self) -> CBC_MAC_R

Bit 15 - 15:15] Set to 1 to select AES-CBC MAC mode. The direction bit must be set to 1 for this mode. Selecting this mode requires writing the length register after all other registers.

pub fn reserved2(&self) -> RESERVED2_R

Bits 9:14 - 14:9] Bits should be written with a value of 0. and ignored on a read.

pub fn ctr_width(&self) -> CTR_WIDTH_R

Bits 7:8 - 8:7] Specifies the counter width for AES-CTR mode 00 = 32-bit counter 01 = 64-bit counter 10 = 96-bit counter 11 = 128-bit counter

pub fn ctr(&self) -> CTR_R

Bit 6 - 6:6] If set to 1, AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required.

pub fn cbc(&self) -> CBC_R

Bit 5 - 5:5] If set to 1, cipher-block-chaining (CBC) mode is selected.

pub fn key_size(&self) -> KEY_SIZE_R

Bits 3:4 - 4:3] This read-only field specifies the key size. The key size is automatically configured when a new key is loaded through the key store module. 00 = N/A - Reserved 01 = 128-bit 10 = 192-bit 11 = 256-bit

pub fn direction(&self) -> DIRECTION_R

Bit 2 - 2:2] If set to 1 an encrypt operation is performed. If set to 0 a decrypt operation is performed. This bit must be written with a 1 when CBC-MAC is selected.

pub fn input_ready(&self) -> INPUT_READY_R

Bit 1 - 1:1] If 1, this status bit indicates that the 16-byte AES input buffer is empty. The host is permitted to write the next block of data. Writing 0 clears the bit to 0 and indicates that the AES core can use the provided input data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. After reset, this bit is 0. After writing a context, this bit becomes 1.

pub fn output_ready(&self) -> OUTPUT_READY_R

Bit 0 - 0:0] If 1, this status bit indicates that an AES output block is available to be retrieved by the host. Writing 0 clears the bit to 0 and indicates that output data is read by the host. The AES core can provide a next output data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t.