1#[doc = "Register `IM` reader"]
2pub type R = crate::R<ImSpec>;
3#[doc = "Register `IM` writer"]
4pub type W = crate::W<ImSpec>;
5#[doc = "Field `RXIM` reader - UART receive interrupt mask 1: An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. 0: The RXRIS interrupt is suppressed and not sent to the interrupt controller."]
6pub type RximR = crate::BitReader;
7#[doc = "Field `RXIM` writer - UART receive interrupt mask 1: An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. 0: The RXRIS interrupt is suppressed and not sent to the interrupt controller."]
8pub type RximW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXIM` reader - UART transmit interrupt mask 1: An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. 0: The TXRIS interrupt is suppressed and not sent to the interrupt controller."]
10pub type TximR = crate::BitReader;
11#[doc = "Field `TXIM` writer - UART transmit interrupt mask 1: An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. 0: The TXRIS interrupt is suppressed and not sent to the interrupt controller."]
12pub type TximW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RTIM` reader - UART receive time-out interrupt mask 1: An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. 0: The RTRIS interrupt is suppressed and not sent to the interrupt controller."]
14pub type RtimR = crate::BitReader;
15#[doc = "Field `RTIM` writer - UART receive time-out interrupt mask 1: An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. 0: The RTRIS interrupt is suppressed and not sent to the interrupt controller."]
16pub type RtimW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FEIM` reader - UART framing error interrupt mask 1: An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. 0: The FERIS interrupt is suppressed and not sent to the interrupt controller."]
18pub type FeimR = crate::BitReader;
19#[doc = "Field `FEIM` writer - UART framing error interrupt mask 1: An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. 0: The FERIS interrupt is suppressed and not sent to the interrupt controller."]
20pub type FeimW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PEIM` reader - UART parity error interrupt mask 1: An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. 0: The PERIS interrupt is suppressed and not sent to the interrupt controller."]
22pub type PeimR = crate::BitReader;
23#[doc = "Field `PEIM` writer - UART parity error interrupt mask 1: An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. 0: The PERIS interrupt is suppressed and not sent to the interrupt controller."]
24pub type PeimW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `BEIM` reader - UART break error interrupt mask 1: An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 0: The BERIS interrupt is suppressed and not sent to the interrupt controller."]
26pub type BeimR = crate::BitReader;
27#[doc = "Field `BEIM` writer - UART break error interrupt mask 1: An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 0: The BERIS interrupt is suppressed and not sent to the interrupt controller."]
28pub type BeimW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OEIM` reader - UART overrun error interrupt mask 1: An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. 0: The OERIS interrupt is suppressed and not sent to the interrupt controller."]
30pub type OeimR = crate::BitReader;
31#[doc = "Field `OEIM` writer - UART overrun error interrupt mask 1: An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. 0: The OERIS interrupt is suppressed and not sent to the interrupt controller."]
32pub type OeimW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `NINEBITIM` reader - 9-bit mode interrupt mask 1: An interrupt is sent to the interrupt controller when the 9BITRIS bit in the UARTRIS register is set. 0: The 9BITRIS interrupt is suppressed and not sent to the interrupt controller."]
34pub type NinebitimR = crate::BitReader;
35#[doc = "Field `NINEBITIM` writer - 9-bit mode interrupt mask 1: An interrupt is sent to the interrupt controller when the 9BITRIS bit in the UARTRIS register is set. 0: The 9BITRIS interrupt is suppressed and not sent to the interrupt controller."]
36pub type NinebitimW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `LMSBIM` reader - LIN mode sync break interrupt mask 1: An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set. 0: The LMSBRIS interrupt is suppressed and not sent to the interrupt controller."]
38pub type LmsbimR = crate::BitReader;
39#[doc = "Field `LMSBIM` writer - LIN mode sync break interrupt mask 1: An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set. 0: The LMSBRIS interrupt is suppressed and not sent to the interrupt controller."]
40pub type LmsbimW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `LME1IM` reader - LIN mode edge 1 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set. 0: The LME1RIS interrupt is suppressed and not sent to the interrupt controller."]
42pub type Lme1imR = crate::BitReader;
43#[doc = "Field `LME1IM` writer - LIN mode edge 1 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set. 0: The LME1RIS interrupt is suppressed and not sent to the interrupt controller."]
44pub type Lme1imW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `LME5IM` reader - LIN mode edge 5 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set. 0: The LME5RIS interrupt is suppressed and not sent to the interrupt controller."]
46pub type Lme5imR = crate::BitReader;
47#[doc = "Field `LME5IM` writer - LIN mode edge 5 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set. 0: The LME5RIS interrupt is suppressed and not sent to the interrupt controller."]
48pub type Lme5imW<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bit 4 - UART receive interrupt mask 1: An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. 0: The RXRIS interrupt is suppressed and not sent to the interrupt controller."]
51 #[inline(always)]
52 pub fn rxim(&self) -> RximR {
53 RximR::new(((self.bits >> 4) & 1) != 0)
54 }
55 #[doc = "Bit 5 - UART transmit interrupt mask 1: An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. 0: The TXRIS interrupt is suppressed and not sent to the interrupt controller."]
56 #[inline(always)]
57 pub fn txim(&self) -> TximR {
58 TximR::new(((self.bits >> 5) & 1) != 0)
59 }
60 #[doc = "Bit 6 - UART receive time-out interrupt mask 1: An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. 0: The RTRIS interrupt is suppressed and not sent to the interrupt controller."]
61 #[inline(always)]
62 pub fn rtim(&self) -> RtimR {
63 RtimR::new(((self.bits >> 6) & 1) != 0)
64 }
65 #[doc = "Bit 7 - UART framing error interrupt mask 1: An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. 0: The FERIS interrupt is suppressed and not sent to the interrupt controller."]
66 #[inline(always)]
67 pub fn feim(&self) -> FeimR {
68 FeimR::new(((self.bits >> 7) & 1) != 0)
69 }
70 #[doc = "Bit 8 - UART parity error interrupt mask 1: An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. 0: The PERIS interrupt is suppressed and not sent to the interrupt controller."]
71 #[inline(always)]
72 pub fn peim(&self) -> PeimR {
73 PeimR::new(((self.bits >> 8) & 1) != 0)
74 }
75 #[doc = "Bit 9 - UART break error interrupt mask 1: An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 0: The BERIS interrupt is suppressed and not sent to the interrupt controller."]
76 #[inline(always)]
77 pub fn beim(&self) -> BeimR {
78 BeimR::new(((self.bits >> 9) & 1) != 0)
79 }
80 #[doc = "Bit 10 - UART overrun error interrupt mask 1: An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. 0: The OERIS interrupt is suppressed and not sent to the interrupt controller."]
81 #[inline(always)]
82 pub fn oeim(&self) -> OeimR {
83 OeimR::new(((self.bits >> 10) & 1) != 0)
84 }
85 #[doc = "Bit 12 - 9-bit mode interrupt mask 1: An interrupt is sent to the interrupt controller when the 9BITRIS bit in the UARTRIS register is set. 0: The 9BITRIS interrupt is suppressed and not sent to the interrupt controller."]
86 #[inline(always)]
87 pub fn ninebitim(&self) -> NinebitimR {
88 NinebitimR::new(((self.bits >> 12) & 1) != 0)
89 }
90 #[doc = "Bit 13 - LIN mode sync break interrupt mask 1: An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set. 0: The LMSBRIS interrupt is suppressed and not sent to the interrupt controller."]
91 #[inline(always)]
92 pub fn lmsbim(&self) -> LmsbimR {
93 LmsbimR::new(((self.bits >> 13) & 1) != 0)
94 }
95 #[doc = "Bit 14 - LIN mode edge 1 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set. 0: The LME1RIS interrupt is suppressed and not sent to the interrupt controller."]
96 #[inline(always)]
97 pub fn lme1im(&self) -> Lme1imR {
98 Lme1imR::new(((self.bits >> 14) & 1) != 0)
99 }
100 #[doc = "Bit 15 - LIN mode edge 5 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set. 0: The LME5RIS interrupt is suppressed and not sent to the interrupt controller."]
101 #[inline(always)]
102 pub fn lme5im(&self) -> Lme5imR {
103 Lme5imR::new(((self.bits >> 15) & 1) != 0)
104 }
105}
106impl W {
107 #[doc = "Bit 4 - UART receive interrupt mask 1: An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. 0: The RXRIS interrupt is suppressed and not sent to the interrupt controller."]
108 #[inline(always)]
109 pub fn rxim(&mut self) -> RximW<ImSpec> {
110 RximW::new(self, 4)
111 }
112 #[doc = "Bit 5 - UART transmit interrupt mask 1: An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. 0: The TXRIS interrupt is suppressed and not sent to the interrupt controller."]
113 #[inline(always)]
114 pub fn txim(&mut self) -> TximW<ImSpec> {
115 TximW::new(self, 5)
116 }
117 #[doc = "Bit 6 - UART receive time-out interrupt mask 1: An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. 0: The RTRIS interrupt is suppressed and not sent to the interrupt controller."]
118 #[inline(always)]
119 pub fn rtim(&mut self) -> RtimW<ImSpec> {
120 RtimW::new(self, 6)
121 }
122 #[doc = "Bit 7 - UART framing error interrupt mask 1: An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. 0: The FERIS interrupt is suppressed and not sent to the interrupt controller."]
123 #[inline(always)]
124 pub fn feim(&mut self) -> FeimW<ImSpec> {
125 FeimW::new(self, 7)
126 }
127 #[doc = "Bit 8 - UART parity error interrupt mask 1: An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. 0: The PERIS interrupt is suppressed and not sent to the interrupt controller."]
128 #[inline(always)]
129 pub fn peim(&mut self) -> PeimW<ImSpec> {
130 PeimW::new(self, 8)
131 }
132 #[doc = "Bit 9 - UART break error interrupt mask 1: An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 0: The BERIS interrupt is suppressed and not sent to the interrupt controller."]
133 #[inline(always)]
134 pub fn beim(&mut self) -> BeimW<ImSpec> {
135 BeimW::new(self, 9)
136 }
137 #[doc = "Bit 10 - UART overrun error interrupt mask 1: An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. 0: The OERIS interrupt is suppressed and not sent to the interrupt controller."]
138 #[inline(always)]
139 pub fn oeim(&mut self) -> OeimW<ImSpec> {
140 OeimW::new(self, 10)
141 }
142 #[doc = "Bit 12 - 9-bit mode interrupt mask 1: An interrupt is sent to the interrupt controller when the 9BITRIS bit in the UARTRIS register is set. 0: The 9BITRIS interrupt is suppressed and not sent to the interrupt controller."]
143 #[inline(always)]
144 pub fn ninebitim(&mut self) -> NinebitimW<ImSpec> {
145 NinebitimW::new(self, 12)
146 }
147 #[doc = "Bit 13 - LIN mode sync break interrupt mask 1: An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set. 0: The LMSBRIS interrupt is suppressed and not sent to the interrupt controller."]
148 #[inline(always)]
149 pub fn lmsbim(&mut self) -> LmsbimW<ImSpec> {
150 LmsbimW::new(self, 13)
151 }
152 #[doc = "Bit 14 - LIN mode edge 1 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set. 0: The LME1RIS interrupt is suppressed and not sent to the interrupt controller."]
153 #[inline(always)]
154 pub fn lme1im(&mut self) -> Lme1imW<ImSpec> {
155 Lme1imW::new(self, 14)
156 }
157 #[doc = "Bit 15 - LIN mode edge 5 interrupt mask 1: An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set. 0: The LME5RIS interrupt is suppressed and not sent to the interrupt controller."]
158 #[inline(always)]
159 pub fn lme5im(&mut self) -> Lme5imW<ImSpec> {
160 Lme5imW::new(self, 15)
161 }
162}
163#[doc = "UART interrupt mask The IM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller.\n\nYou can [`read`](crate::Reg::read) this register and get [`im::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`im::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
164pub struct ImSpec;
165impl crate::RegisterSpec for ImSpec {
166 type Ux = u32;
167}
168#[doc = "`read()` method returns [`im::R`](R) reader structure"]
169impl crate::Readable for ImSpec {}
170#[doc = "`write(|w| ..)` method takes [`im::W`](W) writer structure"]
171impl crate::Writable for ImSpec {
172 type Safety = crate::Unsafe;
173 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
174 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
175}
176#[doc = "`reset()` method sets IM to value 0"]
177impl crate::Resettable for ImSpec {
178 const RESET_VALUE: u32 = 0;
179}