cc2538_pac/aes/
ctrl_options.rs

1#[doc = "Register `CTRL_OPTIONS` reader"]
2pub type R = crate::R<CtrlOptionsSpec>;
3#[doc = "Field `KEYSTORE` reader - KEY STORE is available."]
4pub type KeystoreR = crate::BitReader;
5#[doc = "Field `AES` reader - AES core is available."]
6pub type AesR = crate::BitReader;
7#[doc = "Field `HASH` reader - HASH Core is available."]
8pub type HashR = crate::BitReader;
9#[doc = "Field `AES_128` reader - AES core supports 128-bit keys."]
10pub type Aes128R = crate::BitReader;
11#[doc = "Field `AES_256` reader - AES core supports 256-bit keys Note: If both AES-128 and AES-256 are set to one, the AES core supports 192-bit keys as well."]
12pub type Aes256R = crate::BitReader;
13#[doc = "Field `AES_GCM` reader - AES-GCM is available as a single operation."]
14pub type AesGcmR = crate::BitReader;
15#[doc = "Field `AES_CCM` reader - AES-CCM is available as a single operation."]
16pub type AesCcmR = crate::BitReader;
17#[doc = "Field `SHA_256` reader - The HASH core supports SHA-256."]
18pub type Sha256R = crate::BitReader;
19#[doc = "Field `AHBINTERFACE` reader - AHB interface is available If this bit is 0, the EIP-120t has a TCM interface."]
20pub type AhbinterfaceR = crate::BitReader;
21#[doc = "Field `TYPE` reader - This field is 0x01 for the TYPE1 device."]
22pub type TypeR = crate::FieldReader;
23impl R {
24    #[doc = "Bit 0 - KEY STORE is available."]
25    #[inline(always)]
26    pub fn keystore(&self) -> KeystoreR {
27        KeystoreR::new((self.bits & 1) != 0)
28    }
29    #[doc = "Bit 1 - AES core is available."]
30    #[inline(always)]
31    pub fn aes(&self) -> AesR {
32        AesR::new(((self.bits >> 1) & 1) != 0)
33    }
34    #[doc = "Bit 2 - HASH Core is available."]
35    #[inline(always)]
36    pub fn hash(&self) -> HashR {
37        HashR::new(((self.bits >> 2) & 1) != 0)
38    }
39    #[doc = "Bit 4 - AES core supports 128-bit keys."]
40    #[inline(always)]
41    pub fn aes_128(&self) -> Aes128R {
42        Aes128R::new(((self.bits >> 4) & 1) != 0)
43    }
44    #[doc = "Bit 5 - AES core supports 256-bit keys Note: If both AES-128 and AES-256 are set to one, the AES core supports 192-bit keys as well."]
45    #[inline(always)]
46    pub fn aes_256(&self) -> Aes256R {
47        Aes256R::new(((self.bits >> 5) & 1) != 0)
48    }
49    #[doc = "Bit 6 - AES-GCM is available as a single operation."]
50    #[inline(always)]
51    pub fn aes_gcm(&self) -> AesGcmR {
52        AesGcmR::new(((self.bits >> 6) & 1) != 0)
53    }
54    #[doc = "Bit 7 - AES-CCM is available as a single operation."]
55    #[inline(always)]
56    pub fn aes_ccm(&self) -> AesCcmR {
57        AesCcmR::new(((self.bits >> 7) & 1) != 0)
58    }
59    #[doc = "Bit 8 - The HASH core supports SHA-256."]
60    #[inline(always)]
61    pub fn sha_256(&self) -> Sha256R {
62        Sha256R::new(((self.bits >> 8) & 1) != 0)
63    }
64    #[doc = "Bit 16 - AHB interface is available If this bit is 0, the EIP-120t has a TCM interface."]
65    #[inline(always)]
66    pub fn ahbinterface(&self) -> AhbinterfaceR {
67        AhbinterfaceR::new(((self.bits >> 16) & 1) != 0)
68    }
69    #[doc = "Bits 24:31 - This field is 0x01 for the TYPE1 device."]
70    #[inline(always)]
71    pub fn type_(&self) -> TypeR {
72        TypeR::new(((self.bits >> 24) & 0xff) as u8)
73    }
74}
75#[doc = "Options register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_options::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
76pub struct CtrlOptionsSpec;
77impl crate::RegisterSpec for CtrlOptionsSpec {
78    type Ux = u32;
79}
80#[doc = "`read()` method returns [`ctrl_options::R`](R) reader structure"]
81impl crate::Readable for CtrlOptionsSpec {}
82#[doc = "`reset()` method sets CTRL_OPTIONS to value 0"]
83impl crate::Resettable for CtrlOptionsSpec {
84    const RESET_VALUE: u32 = 0;
85}
cc2538_pac/aes/ctrl_options.rs

cc2538_pac/aes/
ctrl_options.rs
