cc2538_pac/sys_ctrl/
iwe.rs

1#[doc = "Register `IWE` reader"]
2pub type R = crate::R<IweSpec>;
3#[doc = "Register `IWE` writer"]
4pub type W = crate::W<IweSpec>;
5#[doc = "Field `PORT_A_IWE` reader - 1: Enable port A wake-up interrupt. 0: Disable port A wake-up interrupt."]
6pub type PortAIweR = crate::BitReader;
7#[doc = "Field `PORT_A_IWE` writer - 1: Enable port A wake-up interrupt. 0: Disable port A wake-up interrupt."]
8pub type PortAIweW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PORT_B_IWE` reader - 1: Enable port B wake-up interrupt. 0: Disable port B wake-up interrupt."]
10pub type PortBIweR = crate::BitReader;
11#[doc = "Field `PORT_B_IWE` writer - 1: Enable port B wake-up interrupt. 0: Disable port B wake-up interrupt."]
12pub type PortBIweW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PORT_C_IWE` reader - 1: Enable port C wake-up interrupt. 0: Disable port C wake-up interrupt."]
14pub type PortCIweR = crate::BitReader;
15#[doc = "Field `PORT_C_IWE` writer - 1: Enable port C wake-up interrupt. 0: Disable port C wake-up interrupt."]
16pub type PortCIweW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PORT_D_IWE` reader - 1: Enable port D wake-up interrupt. 0: Disable port D wake-up interrupt."]
18pub type PortDIweR = crate::BitReader;
19#[doc = "Field `PORT_D_IWE` writer - 1: Enable port D wake-up interrupt. 0: Disable port D wake-up interrupt."]
20pub type PortDIweW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `USB_IWE` reader - 1: Enable USB wake-up interrupt. 0: Disable USB wake-up interrupt."]
22pub type UsbIweR = crate::BitReader;
23#[doc = "Field `USB_IWE` writer - 1: Enable USB wake-up interrupt. 0: Disable USB wake-up interrupt."]
24pub type UsbIweW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SM_TIMER_IWE` reader - 1: Enable SM Timer wake-up interrupt. 0: Disable SM Timer wake-up interrupt."]
26pub type SmTimerIweR = crate::BitReader;
27#[doc = "Field `SM_TIMER_IWE` writer - 1: Enable SM Timer wake-up interrupt. 0: Disable SM Timer wake-up interrupt."]
28pub type SmTimerIweW<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - 1: Enable port A wake-up interrupt. 0: Disable port A wake-up interrupt."]
31    #[inline(always)]
32    pub fn port_a_iwe(&self) -> PortAIweR {
33        PortAIweR::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - 1: Enable port B wake-up interrupt. 0: Disable port B wake-up interrupt."]
36    #[inline(always)]
37    pub fn port_b_iwe(&self) -> PortBIweR {
38        PortBIweR::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - 1: Enable port C wake-up interrupt. 0: Disable port C wake-up interrupt."]
41    #[inline(always)]
42    pub fn port_c_iwe(&self) -> PortCIweR {
43        PortCIweR::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - 1: Enable port D wake-up interrupt. 0: Disable port D wake-up interrupt."]
46    #[inline(always)]
47    pub fn port_d_iwe(&self) -> PortDIweR {
48        PortDIweR::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - 1: Enable USB wake-up interrupt. 0: Disable USB wake-up interrupt."]
51    #[inline(always)]
52    pub fn usb_iwe(&self) -> UsbIweR {
53        UsbIweR::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - 1: Enable SM Timer wake-up interrupt. 0: Disable SM Timer wake-up interrupt."]
56    #[inline(always)]
57    pub fn sm_timer_iwe(&self) -> SmTimerIweR {
58        SmTimerIweR::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - 1: Enable port A wake-up interrupt. 0: Disable port A wake-up interrupt."]
63    #[inline(always)]
64    pub fn port_a_iwe(&mut self) -> PortAIweW<IweSpec> {
65        PortAIweW::new(self, 0)
66    }
67    #[doc = "Bit 1 - 1: Enable port B wake-up interrupt. 0: Disable port B wake-up interrupt."]
68    #[inline(always)]
69    pub fn port_b_iwe(&mut self) -> PortBIweW<IweSpec> {
70        PortBIweW::new(self, 1)
71    }
72    #[doc = "Bit 2 - 1: Enable port C wake-up interrupt. 0: Disable port C wake-up interrupt."]
73    #[inline(always)]
74    pub fn port_c_iwe(&mut self) -> PortCIweW<IweSpec> {
75        PortCIweW::new(self, 2)
76    }
77    #[doc = "Bit 3 - 1: Enable port D wake-up interrupt. 0: Disable port D wake-up interrupt."]
78    #[inline(always)]
79    pub fn port_d_iwe(&mut self) -> PortDIweW<IweSpec> {
80        PortDIweW::new(self, 3)
81    }
82    #[doc = "Bit 4 - 1: Enable USB wake-up interrupt. 0: Disable USB wake-up interrupt."]
83    #[inline(always)]
84    pub fn usb_iwe(&mut self) -> UsbIweW<IweSpec> {
85        UsbIweW::new(self, 4)
86    }
87    #[doc = "Bit 5 - 1: Enable SM Timer wake-up interrupt. 0: Disable SM Timer wake-up interrupt."]
88    #[inline(always)]
89    pub fn sm_timer_iwe(&mut self) -> SmTimerIweW<IweSpec> {
90        SmTimerIweW::new(self, 5)
91    }
92}
93#[doc = "This register controls interrupt wake-up.\n\nYou can [`read`](crate::Reg::read) this register and get [`iwe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iwe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
94pub struct IweSpec;
95impl crate::RegisterSpec for IweSpec {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [`iwe::R`](R) reader structure"]
99impl crate::Readable for IweSpec {}
100#[doc = "`write(|w| ..)` method takes [`iwe::W`](W) writer structure"]
101impl crate::Writable for IweSpec {
102    type Safety = crate::Unsafe;
103    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
104    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
105}
106#[doc = "`reset()` method sets IWE to value 0"]
107impl crate::Resettable for IweSpec {
108    const RESET_VALUE: u32 = 0;
109}
cc2538_pac/sys_ctrl/iwe.rs

cc2538_pac/sys_ctrl/
iwe.rs
