cc2538_pac/gptimer1/
tamr.rs

1#[doc = "Register `TAMR` reader"]
2pub type R = crate::R<TamrSpec>;
3#[doc = "Register `TAMR` writer"]
4pub type W = crate::W<TamrSpec>;
5#[doc = "Field `TAMR` reader - GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits \\[2:0\\]
6in the GPTMCFG register."]
7pub type TamrR = crate::FieldReader;
8#[doc = "Field `TAMR` writer - GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits \\[2:0\\]
9in the GPTMCFG register."]
10pub type TamrW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
11#[doc = "Field `TACMR` reader - GPTM Timer A capture mode 0: Edge-count mode 1: Edge-time mode"]
12pub type TacmrR = crate::BitReader;
13#[doc = "Field `TACMR` writer - GPTM Timer A capture mode 0: Edge-count mode 1: Edge-time mode"]
14pub type TacmrW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `TAAMS` reader - GPTM Timer A alternate mode 0: Capture mode is enabled. 1: PWM mode is enabled. Note: To enable PWM mode, the TACM bit must be cleared and the TAMR field must be configured to 0x2."]
16pub type TaamsR = crate::BitReader;
17#[doc = "Field `TAAMS` writer - GPTM Timer A alternate mode 0: Capture mode is enabled. 1: PWM mode is enabled. Note: To enable PWM mode, the TACM bit must be cleared and the TAMR field must be configured to 0x2."]
18pub type TaamsW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `TACDIR` reader - GPTM Timer A count direction 0: The timer counts down. 1: The timer counts up. When counting up, the timer starts from a value of 0x0."]
20pub type TacdirR = crate::BitReader;
21#[doc = "Field `TACDIR` writer - GPTM Timer A count direction 0: The timer counts down. 1: The timer counts up. When counting up, the timer starts from a value of 0x0."]
22pub type TacdirW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `TAMIE` reader - GPTM Timer A match interrupt enable 0: The match interrupt is disabled. 1: An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes."]
24pub type TamieR = crate::BitReader;
25#[doc = "Field `TAMIE` writer - GPTM Timer A match interrupt enable 0: The match interrupt is disabled. 1: An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes."]
26pub type TamieW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `TAWOT` reader - GPTM Timer A wait-on-trigger 0: Timer A begins counting as soon as it is enabled. 1: If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the Timer in the previous position in the daisy-chain. This bit must be clear for GP Timer module 0, Timer A."]
28pub type TawotR = crate::BitReader;
29#[doc = "Field `TAWOT` writer - GPTM Timer A wait-on-trigger 0: Timer A begins counting as soon as it is enabled. 1: If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the Timer in the previous position in the daisy-chain. This bit must be clear for GP Timer module 0, Timer A."]
30pub type TawotW<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `TASNAPS` reader - GPTM Timer A snap-shot mode 0: Snap-shot mode is disabled. 1: If Timer A is configured in periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPTM Timer A (GPTMTAR) register."]
32pub type TasnapsR = crate::BitReader;
33#[doc = "Field `TASNAPS` writer - GPTM Timer A snap-shot mode 0: Snap-shot mode is disabled. 1: If Timer A is configured in periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPTM Timer A (GPTMTAR) register."]
34pub type TasnapsW<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `TAILD` reader - GPTM Timer A PWM interval load write 0: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle. 1: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next time-out."]
36pub type TaildR = crate::BitReader;
37#[doc = "Field `TAILD` writer - GPTM Timer A PWM interval load write 0: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle. 1: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next time-out."]
38pub type TaildW<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `TAPWMIE` reader - GPTM Timer A PWM interrupt enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output. 0: Interrupt is disabled. 1: Interrupt is enabled. This bit is valid only in PWM mode."]
40pub type TapwmieR = crate::BitReader;
41#[doc = "Field `TAPWMIE` writer - GPTM Timer A PWM interrupt enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output. 0: Interrupt is disabled. 1: Interrupt is enabled. This bit is valid only in PWM mode."]
42pub type TapwmieW<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `TAMRSU` reader - Timer A match register update mode 0: Update GPTMAMATCHR and GPTMAPR if used on the next cycle. 1: Update GPTMAMATCHR and GPTMAPR if used on the next time-out. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit."]
44pub type TamrsuR = crate::BitReader;
45#[doc = "Field `TAMRSU` writer - Timer A match register update mode 0: Update GPTMAMATCHR and GPTMAPR if used on the next cycle. 1: Update GPTMAMATCHR and GPTMAPR if used on the next time-out. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit."]
46pub type TamrsuW<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `TAPLO` reader - Legacy PWM operation 0: Legacy operation 1: CCP is set to 1 on time-out."]
48pub type TaploR = crate::BitReader;
49#[doc = "Field `TAPLO` writer - Legacy PWM operation 0: Legacy operation 1: CCP is set to 1 on time-out."]
50pub type TaploW<'a, REG> = crate::BitWriter<'a, REG>;
51impl R {
52    #[doc = "Bits 0:1 - GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits \\[2:0\\]
53in the GPTMCFG register."]
54    #[inline(always)]
55    pub fn tamr(&self) -> TamrR {
56        TamrR::new((self.bits & 3) as u8)
57    }
58    #[doc = "Bit 2 - GPTM Timer A capture mode 0: Edge-count mode 1: Edge-time mode"]
59    #[inline(always)]
60    pub fn tacmr(&self) -> TacmrR {
61        TacmrR::new(((self.bits >> 2) & 1) != 0)
62    }
63    #[doc = "Bit 3 - GPTM Timer A alternate mode 0: Capture mode is enabled. 1: PWM mode is enabled. Note: To enable PWM mode, the TACM bit must be cleared and the TAMR field must be configured to 0x2."]
64    #[inline(always)]
65    pub fn taams(&self) -> TaamsR {
66        TaamsR::new(((self.bits >> 3) & 1) != 0)
67    }
68    #[doc = "Bit 4 - GPTM Timer A count direction 0: The timer counts down. 1: The timer counts up. When counting up, the timer starts from a value of 0x0."]
69    #[inline(always)]
70    pub fn tacdir(&self) -> TacdirR {
71        TacdirR::new(((self.bits >> 4) & 1) != 0)
72    }
73    #[doc = "Bit 5 - GPTM Timer A match interrupt enable 0: The match interrupt is disabled. 1: An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes."]
74    #[inline(always)]
75    pub fn tamie(&self) -> TamieR {
76        TamieR::new(((self.bits >> 5) & 1) != 0)
77    }
78    #[doc = "Bit 6 - GPTM Timer A wait-on-trigger 0: Timer A begins counting as soon as it is enabled. 1: If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the Timer in the previous position in the daisy-chain. This bit must be clear for GP Timer module 0, Timer A."]
79    #[inline(always)]
80    pub fn tawot(&self) -> TawotR {
81        TawotR::new(((self.bits >> 6) & 1) != 0)
82    }
83    #[doc = "Bit 7 - GPTM Timer A snap-shot mode 0: Snap-shot mode is disabled. 1: If Timer A is configured in periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPTM Timer A (GPTMTAR) register."]
84    #[inline(always)]
85    pub fn tasnaps(&self) -> TasnapsR {
86        TasnapsR::new(((self.bits >> 7) & 1) != 0)
87    }
88    #[doc = "Bit 8 - GPTM Timer A PWM interval load write 0: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle. 1: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next time-out."]
89    #[inline(always)]
90    pub fn taild(&self) -> TaildR {
91        TaildR::new(((self.bits >> 8) & 1) != 0)
92    }
93    #[doc = "Bit 9 - GPTM Timer A PWM interrupt enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output. 0: Interrupt is disabled. 1: Interrupt is enabled. This bit is valid only in PWM mode."]
94    #[inline(always)]
95    pub fn tapwmie(&self) -> TapwmieR {
96        TapwmieR::new(((self.bits >> 9) & 1) != 0)
97    }
98    #[doc = "Bit 10 - Timer A match register update mode 0: Update GPTMAMATCHR and GPTMAPR if used on the next cycle. 1: Update GPTMAMATCHR and GPTMAPR if used on the next time-out. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit."]
99    #[inline(always)]
100    pub fn tamrsu(&self) -> TamrsuR {
101        TamrsuR::new(((self.bits >> 10) & 1) != 0)
102    }
103    #[doc = "Bit 11 - Legacy PWM operation 0: Legacy operation 1: CCP is set to 1 on time-out."]
104    #[inline(always)]
105    pub fn taplo(&self) -> TaploR {
106        TaploR::new(((self.bits >> 11) & 1) != 0)
107    }
108}
109impl W {
110    #[doc = "Bits 0:1 - GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits \\[2:0\\]
111in the GPTMCFG register."]
112    #[inline(always)]
113    pub fn tamr(&mut self) -> TamrW<TamrSpec> {
114        TamrW::new(self, 0)
115    }
116    #[doc = "Bit 2 - GPTM Timer A capture mode 0: Edge-count mode 1: Edge-time mode"]
117    #[inline(always)]
118    pub fn tacmr(&mut self) -> TacmrW<TamrSpec> {
119        TacmrW::new(self, 2)
120    }
121    #[doc = "Bit 3 - GPTM Timer A alternate mode 0: Capture mode is enabled. 1: PWM mode is enabled. Note: To enable PWM mode, the TACM bit must be cleared and the TAMR field must be configured to 0x2."]
122    #[inline(always)]
123    pub fn taams(&mut self) -> TaamsW<TamrSpec> {
124        TaamsW::new(self, 3)
125    }
126    #[doc = "Bit 4 - GPTM Timer A count direction 0: The timer counts down. 1: The timer counts up. When counting up, the timer starts from a value of 0x0."]
127    #[inline(always)]
128    pub fn tacdir(&mut self) -> TacdirW<TamrSpec> {
129        TacdirW::new(self, 4)
130    }
131    #[doc = "Bit 5 - GPTM Timer A match interrupt enable 0: The match interrupt is disabled. 1: An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes."]
132    #[inline(always)]
133    pub fn tamie(&mut self) -> TamieW<TamrSpec> {
134        TamieW::new(self, 5)
135    }
136    #[doc = "Bit 6 - GPTM Timer A wait-on-trigger 0: Timer A begins counting as soon as it is enabled. 1: If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the Timer in the previous position in the daisy-chain. This bit must be clear for GP Timer module 0, Timer A."]
137    #[inline(always)]
138    pub fn tawot(&mut self) -> TawotW<TamrSpec> {
139        TawotW::new(self, 6)
140    }
141    #[doc = "Bit 7 - GPTM Timer A snap-shot mode 0: Snap-shot mode is disabled. 1: If Timer A is configured in periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPTM Timer A (GPTMTAR) register."]
142    #[inline(always)]
143    pub fn tasnaps(&mut self) -> TasnapsW<TamrSpec> {
144        TasnapsW::new(self, 7)
145    }
146    #[doc = "Bit 8 - GPTM Timer A PWM interval load write 0: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle. 1: Update the GPTMTAR register with the value in the GPTMTAILR register on the next cycle. If the prescaler is used, update the GPTMTAPS register with the value in the GPTMTAPR register on the next time-out."]
147    #[inline(always)]
148    pub fn taild(&mut self) -> TaildW<TamrSpec> {
149        TaildW::new(self, 8)
150    }
151    #[doc = "Bit 9 - GPTM Timer A PWM interrupt enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output. 0: Interrupt is disabled. 1: Interrupt is enabled. This bit is valid only in PWM mode."]
152    #[inline(always)]
153    pub fn tapwmie(&mut self) -> TapwmieW<TamrSpec> {
154        TapwmieW::new(self, 9)
155    }
156    #[doc = "Bit 10 - Timer A match register update mode 0: Update GPTMAMATCHR and GPTMAPR if used on the next cycle. 1: Update GPTMAMATCHR and GPTMAPR if used on the next time-out. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit."]
157    #[inline(always)]
158    pub fn tamrsu(&mut self) -> TamrsuW<TamrSpec> {
159        TamrsuW::new(self, 10)
160    }
161    #[doc = "Bit 11 - Legacy PWM operation 0: Legacy operation 1: CCP is set to 1 on time-out."]
162    #[inline(always)]
163    pub fn taplo(&mut self) -> TaploW<TamrSpec> {
164        TaploW::new(self, 11)
165    }
166}
167#[doc = "GPTM Timer A mode This register configures the GPTM based on the configuration selected in the CFG register. This register controls the modes for Timer A when it is used individually. When Timer A and Timer B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents of TBMR are ignored.\n\nYou can [`read`](crate::Reg::read) this register and get [`tamr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tamr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
168pub struct TamrSpec;
169impl crate::RegisterSpec for TamrSpec {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [`tamr::R`](R) reader structure"]
173impl crate::Readable for TamrSpec {}
174#[doc = "`write(|w| ..)` method takes [`tamr::W`](W) writer structure"]
175impl crate::Writable for TamrSpec {
176    type Safety = crate::Unsafe;
177    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
179}
180#[doc = "`reset()` method sets TAMR to value 0"]
181impl crate::Resettable for TamrSpec {
182    const RESET_VALUE: u32 = 0;
183}
cc2538_pac/gptimer1/tamr.rs

cc2538_pac/gptimer1/
tamr.rs
