cc2538_pac/flash_ctrl/
fctl.rs

1#[doc = "Register `FCTL` reader"]
2pub type R = crate::R<FctlSpec>;
3#[doc = "Register `FCTL` writer"]
4pub type W = crate::W<FctlSpec>;
5#[doc = "Field `ERASE` reader - Erase bit Start an erase operation by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.WRITE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
6pub type EraseR = crate::BitReader;
7#[doc = "Field `ERASE` writer - Erase bit Start an erase operation by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.WRITE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
8pub type EraseW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `WRITE` reader - Write bit Start a write sequence by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.ERASE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
10pub type WriteR = crate::BitReader;
11#[doc = "Field `WRITE` writer - Write bit Start a write sequence by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.ERASE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
12pub type WriteW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CM` reader - Cache Mode Disabling the cache increases the power consumption and reduces performance. Prefetching improves performance at the expense of a potential increase in power consumption. Real-time mode provides predictable flash read access time, the execution time is equal to cache disabled mode, but the power consumption is lower. 00: Cache disabled 01: Cache enabled 10: Cache enabled, with prefetch 11: Real-time mode Note: The read value always represents the current cache mode. Writing a new cache mode starts a cache mode change request that does not take effect until the controller is ready. Writes to this register are ignored if there is a current cache change request in progress."]
14pub type CmR = crate::FieldReader;
15#[doc = "Field `CM` writer - Cache Mode Disabling the cache increases the power consumption and reduces performance. Prefetching improves performance at the expense of a potential increase in power consumption. Real-time mode provides predictable flash read access time, the execution time is equal to cache disabled mode, but the power consumption is lower. 00: Cache disabled 01: Cache enabled 10: Cache enabled, with prefetch 11: Real-time mode Note: The read value always represents the current cache mode. Writing a new cache mode starts a cache mode change request that does not take effect until the controller is ready. Writes to this register are ignored if there is a current cache change request in progress."]
16pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `ABORT` reader - Abort status This bit is set to 1 when a write sequence or page erase is aborted. An operation is aborted when the accessed page is locked. Cleared when a write or page erase is started. If a write operation times out (because the FWDATA register is not written fast enough), the ABORT bit is not set even if the page is locked. If a page erase and a write operation are started simultaneously, the ABORT bit reflects the status of the last write operation. For example, if the page is locked and the write times out, the ABORT bit is not set because only the write operation times out."]
18pub type AbortR = crate::BitReader;
19#[doc = "Field `FULL` reader - Write buffer full The CPU can write to FWDATA when this bit is 0 and WRITE is 1. This bit is cleared when BUSY is cleared."]
20pub type FullR = crate::BitReader;
21#[doc = "Field `BUSY` reader - Set when the WRITE or ERASE bit is set; that is, when the flash controller is busy"]
22pub type BusyR = crate::BitReader;
23#[doc = "Field `SEL_INFO_PAGE` reader - Flash erase or write operation on APB bus must assert this when accessing the information page"]
24pub type SelInfoPageR = crate::BitReader;
25#[doc = "Field `SEL_INFO_PAGE` writer - Flash erase or write operation on APB bus must assert this when accessing the information page"]
26pub type SelInfoPageW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `UPPER_PAGE_ACCESS` reader - Lock bit for lock bit page 0: Neither write nor erase not allowed 1: Both write and erase allowed"]
28pub type UpperPageAccessR = crate::BitReader;
29#[doc = "Field `UPPER_PAGE_ACCESS` writer - Lock bit for lock bit page 0: Neither write nor erase not allowed 1: Both write and erase allowed"]
30pub type UpperPageAccessW<'a, REG> = crate::BitWriter<'a, REG>;
31impl R {
32    #[doc = "Bit 0 - Erase bit Start an erase operation by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.WRITE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
33    #[inline(always)]
34    pub fn erase(&self) -> EraseR {
35        EraseR::new((self.bits & 1) != 0)
36    }
37    #[doc = "Bit 1 - Write bit Start a write sequence by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.ERASE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
38    #[inline(always)]
39    pub fn write(&self) -> WriteR {
40        WriteR::new(((self.bits >> 1) & 1) != 0)
41    }
42    #[doc = "Bits 2:3 - Cache Mode Disabling the cache increases the power consumption and reduces performance. Prefetching improves performance at the expense of a potential increase in power consumption. Real-time mode provides predictable flash read access time, the execution time is equal to cache disabled mode, but the power consumption is lower. 00: Cache disabled 01: Cache enabled 10: Cache enabled, with prefetch 11: Real-time mode Note: The read value always represents the current cache mode. Writing a new cache mode starts a cache mode change request that does not take effect until the controller is ready. Writes to this register are ignored if there is a current cache change request in progress."]
43    #[inline(always)]
44    pub fn cm(&self) -> CmR {
45        CmR::new(((self.bits >> 2) & 3) as u8)
46    }
47    #[doc = "Bit 5 - Abort status This bit is set to 1 when a write sequence or page erase is aborted. An operation is aborted when the accessed page is locked. Cleared when a write or page erase is started. If a write operation times out (because the FWDATA register is not written fast enough), the ABORT bit is not set even if the page is locked. If a page erase and a write operation are started simultaneously, the ABORT bit reflects the status of the last write operation. For example, if the page is locked and the write times out, the ABORT bit is not set because only the write operation times out."]
48    #[inline(always)]
49    pub fn abort(&self) -> AbortR {
50        AbortR::new(((self.bits >> 5) & 1) != 0)
51    }
52    #[doc = "Bit 6 - Write buffer full The CPU can write to FWDATA when this bit is 0 and WRITE is 1. This bit is cleared when BUSY is cleared."]
53    #[inline(always)]
54    pub fn full(&self) -> FullR {
55        FullR::new(((self.bits >> 6) & 1) != 0)
56    }
57    #[doc = "Bit 7 - Set when the WRITE or ERASE bit is set; that is, when the flash controller is busy"]
58    #[inline(always)]
59    pub fn busy(&self) -> BusyR {
60        BusyR::new(((self.bits >> 7) & 1) != 0)
61    }
62    #[doc = "Bit 8 - Flash erase or write operation on APB bus must assert this when accessing the information page"]
63    #[inline(always)]
64    pub fn sel_info_page(&self) -> SelInfoPageR {
65        SelInfoPageR::new(((self.bits >> 8) & 1) != 0)
66    }
67    #[doc = "Bit 9 - Lock bit for lock bit page 0: Neither write nor erase not allowed 1: Both write and erase allowed"]
68    #[inline(always)]
69    pub fn upper_page_access(&self) -> UpperPageAccessR {
70        UpperPageAccessR::new(((self.bits >> 9) & 1) != 0)
71    }
72}
73impl W {
74    #[doc = "Bit 0 - Erase bit Start an erase operation by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.WRITE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
75    #[inline(always)]
76    pub fn erase(&mut self) -> EraseW<FctlSpec> {
77        EraseW::new(self, 0)
78    }
79    #[doc = "Bit 1 - Write bit Start a write sequence by setting this bit to 1. Cleared by hardware when the operation completes. Writes to this bit are ignored when FCTL.BUSY is 1. If FCTL.ERASE is set simultaneously with this bit, the erase operation is started first, then the write is started."]
80    #[inline(always)]
81    pub fn write(&mut self) -> WriteW<FctlSpec> {
82        WriteW::new(self, 1)
83    }
84    #[doc = "Bits 2:3 - Cache Mode Disabling the cache increases the power consumption and reduces performance. Prefetching improves performance at the expense of a potential increase in power consumption. Real-time mode provides predictable flash read access time, the execution time is equal to cache disabled mode, but the power consumption is lower. 00: Cache disabled 01: Cache enabled 10: Cache enabled, with prefetch 11: Real-time mode Note: The read value always represents the current cache mode. Writing a new cache mode starts a cache mode change request that does not take effect until the controller is ready. Writes to this register are ignored if there is a current cache change request in progress."]
85    #[inline(always)]
86    pub fn cm(&mut self) -> CmW<FctlSpec> {
87        CmW::new(self, 2)
88    }
89    #[doc = "Bit 8 - Flash erase or write operation on APB bus must assert this when accessing the information page"]
90    #[inline(always)]
91    pub fn sel_info_page(&mut self) -> SelInfoPageW<FctlSpec> {
92        SelInfoPageW::new(self, 8)
93    }
94    #[doc = "Bit 9 - Lock bit for lock bit page 0: Neither write nor erase not allowed 1: Both write and erase allowed"]
95    #[inline(always)]
96    pub fn upper_page_access(&mut self) -> UpperPageAccessW<FctlSpec> {
97        UpperPageAccessW::new(self, 9)
98    }
99}
100#[doc = "Flash control This register provides control and monitoring functions for the flash module.\n\nYou can [`read`](crate::Reg::read) this register and get [`fctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
101pub struct FctlSpec;
102impl crate::RegisterSpec for FctlSpec {
103    type Ux = u32;
104}
105#[doc = "`read()` method returns [`fctl::R`](R) reader structure"]
106impl crate::Readable for FctlSpec {}
107#[doc = "`write(|w| ..)` method takes [`fctl::W`](W) writer structure"]
108impl crate::Writable for FctlSpec {
109    type Safety = crate::Unsafe;
110    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
112}
113#[doc = "`reset()` method sets FCTL to value 0"]
114impl crate::Resettable for FctlSpec {
115    const RESET_VALUE: u32 = 0;
116}
cc2538_pac/flash_ctrl/fctl.rs

cc2538_pac/flash_ctrl/
fctl.rs
