1#[doc = "Register `CR1` reader"]
2pub type R = crate::R<Cr1Spec>;
3#[doc = "Register `CR1` writer"]
4pub type W = crate::W<Cr1Spec>;
5#[doc = "Field `LBM` reader - SSI loop-back mode (R/W) Reset value: 0x0 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally."]
6pub type LbmR = crate::BitReader;
7#[doc = "Field `LBM` writer - SSI loop-back mode (R/W) Reset value: 0x0 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally."]
8pub type LbmW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SSE` reader - SSI synchronous serial port enable (R/W) Reset value: 0x0 0: SSI operation is disabled. 1: SSI operation is enabled."]
10pub type SseR = crate::BitReader;
11#[doc = "Field `SSE` writer - SSI synchronous serial port enable (R/W) Reset value: 0x0 0: SSI operation is disabled. 1: SSI operation is enabled."]
12pub type SseW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MS` reader - SSI master and slave select (R/W) Reset value: 0x0 This bit can be modified only when the SSI is disabled (SSE = 0). 0: Device configured as a master (default) 1: Device configured as a slave"]
14pub type MsR = crate::BitReader;
15#[doc = "Field `MS` writer - SSI master and slave select (R/W) Reset value: 0x0 This bit can be modified only when the SSI is disabled (SSE = 0). 0: Device configured as a master (default) 1: Device configured as a slave"]
16pub type MsW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SOD` reader - SSI slave mode output disable (R/W) Reset value: 0x0 This bit is relevant only in the slave mode (MS = 1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the RXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be set if the SSI slave is not suppose to drive the SSITXD line. 0: SSI can drive SSITXD in slave output mode 1: SSI must not drive the SSITXD output in slave mode"]
18pub type SodR = crate::BitReader;
19#[doc = "Field `SOD` writer - SSI slave mode output disable (R/W) Reset value: 0x0 This bit is relevant only in the slave mode (MS = 1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the RXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be set if the SSI slave is not suppose to drive the SSITXD line. 0: SSI can drive SSITXD in slave output mode 1: SSI must not drive the SSITXD output in slave mode"]
20pub type SodW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22 #[doc = "Bit 0 - SSI loop-back mode (R/W) Reset value: 0x0 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally."]
23 #[inline(always)]
24 pub fn lbm(&self) -> LbmR {
25 LbmR::new((self.bits & 1) != 0)
26 }
27 #[doc = "Bit 1 - SSI synchronous serial port enable (R/W) Reset value: 0x0 0: SSI operation is disabled. 1: SSI operation is enabled."]
28 #[inline(always)]
29 pub fn sse(&self) -> SseR {
30 SseR::new(((self.bits >> 1) & 1) != 0)
31 }
32 #[doc = "Bit 2 - SSI master and slave select (R/W) Reset value: 0x0 This bit can be modified only when the SSI is disabled (SSE = 0). 0: Device configured as a master (default) 1: Device configured as a slave"]
33 #[inline(always)]
34 pub fn ms(&self) -> MsR {
35 MsR::new(((self.bits >> 2) & 1) != 0)
36 }
37 #[doc = "Bit 3 - SSI slave mode output disable (R/W) Reset value: 0x0 This bit is relevant only in the slave mode (MS = 1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the RXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be set if the SSI slave is not suppose to drive the SSITXD line. 0: SSI can drive SSITXD in slave output mode 1: SSI must not drive the SSITXD output in slave mode"]
38 #[inline(always)]
39 pub fn sod(&self) -> SodR {
40 SodR::new(((self.bits >> 3) & 1) != 0)
41 }
42}
43impl W {
44 #[doc = "Bit 0 - SSI loop-back mode (R/W) Reset value: 0x0 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally."]
45 #[inline(always)]
46 pub fn lbm(&mut self) -> LbmW<Cr1Spec> {
47 LbmW::new(self, 0)
48 }
49 #[doc = "Bit 1 - SSI synchronous serial port enable (R/W) Reset value: 0x0 0: SSI operation is disabled. 1: SSI operation is enabled."]
50 #[inline(always)]
51 pub fn sse(&mut self) -> SseW<Cr1Spec> {
52 SseW::new(self, 1)
53 }
54 #[doc = "Bit 2 - SSI master and slave select (R/W) Reset value: 0x0 This bit can be modified only when the SSI is disabled (SSE = 0). 0: Device configured as a master (default) 1: Device configured as a slave"]
55 #[inline(always)]
56 pub fn ms(&mut self) -> MsW<Cr1Spec> {
57 MsW::new(self, 2)
58 }
59 #[doc = "Bit 3 - SSI slave mode output disable (R/W) Reset value: 0x0 This bit is relevant only in the slave mode (MS = 1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the RXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be set if the SSI slave is not suppose to drive the SSITXD line. 0: SSI can drive SSITXD in slave output mode 1: SSI must not drive the SSITXD output in slave mode"]
60 #[inline(always)]
61 pub fn sod(&mut self) -> SodW<Cr1Spec> {
62 SodW::new(self, 3)
63 }
64}
65#[doc = "The CR1 register contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
66pub struct Cr1Spec;
67impl crate::RegisterSpec for Cr1Spec {
68 type Ux = u32;
69}
70#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
71impl crate::Readable for Cr1Spec {}
72#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
73impl crate::Writable for Cr1Spec {
74 type Safety = crate::Unsafe;
75 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
77}
78#[doc = "`reset()` method sets CR1 to value 0"]
79impl crate::Resettable for Cr1Spec {
80 const RESET_VALUE: u32 = 0;
81}