cc13x2/
lib.rs

1#![doc = "Peripheral access API for CC2652 microcontrollers (generated using svd2rust v0.17.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.17.0/svd2rust/#peripheral-api"]
2#![deny(const_err)]
3#![allow(dead_code)]
4#![deny(improper_ctypes)]
5#![deny(legacy_directory_ownership)]
6#![deny(missing_docs)]
7#![deny(no_mangle_generic_items)]
8#![deny(non_shorthand_field_patterns)]
9#![deny(overflowing_literals)]
10#![deny(path_statements)]
11#![deny(patterns_in_fns_without_body)]
12#![deny(plugin_as_library)]
13#![deny(private_in_public)]
14#![deny(safe_extern_statics)]
15#![deny(unconditional_recursion)]
16#![deny(unions_with_drop_fields)]
17#![deny(unused_allocation)]
18#![deny(unused_comparisons)]
19#![deny(unused_parens)]
20#![deny(while_true)]
21#![allow(non_camel_case_types)]
22#![allow(non_snake_case)]
23#![no_std]
24extern crate bare_metal;
25extern crate cortex_m;
26#[cfg(feature = "rt")]
27extern crate cortex_m_rt;
28extern crate vcell;
29use core::marker::PhantomData;
30use core::ops::Deref;
31#[doc = r"Number available in the NVIC for configuring priority"]
32pub const NVIC_PRIO_BITS: u8 = 3;
33#[cfg(feature = "rt")]
34extern "C" {}
35#[doc(hidden)]
36pub union Vector {
37    _handler: unsafe extern "C" fn(),
38    _reserved: u32,
39}
40#[cfg(feature = "rt")]
41#[doc(hidden)]
42#[link_section = ".vector_table.interrupts"]
43#[no_mangle]
44pub static __INTERRUPTS: [Vector; 0] = [];
45#[doc = r"Enumeration of all the interrupts"]
46#[derive(Copy, Clone, Debug)]
47pub enum Interrupt {}
48unsafe impl bare_metal::Nr for Interrupt {
49    #[inline(always)]
50    fn nr(&self) -> u8 {
51        match *self {}
52    }
53}
54#[cfg(feature = "rt")]
55pub use self::Interrupt as interrupt;
56pub use cortex_m::peripheral::Peripherals as CorePeripherals;
57pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
58#[cfg(feature = "rt")]
59pub use cortex_m_rt::interrupt;
60#[allow(unused_imports)]
61use generic::*;
62#[doc = r"Common register and bit access and modify traits"]
63pub mod generic;
64#[doc = "Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic)"]
65pub struct AUX_ADI4 {
66    _marker: PhantomData<*const ()>,
67}
68unsafe impl Send for AUX_ADI4 {}
69#[cfg(feature = "aux_adi4")]
70impl AUX_ADI4 {
71    #[doc = r"Returns a pointer to the register block"]
72    #[inline(always)]
73    pub const fn ptr() -> *const aux_adi4::RegisterBlock {
74        0x400c_b000 as *const _
75    }
76}
77#[cfg(feature = "aux_adi4")]
78impl Deref for AUX_ADI4 {
79    type Target = aux_adi4::RegisterBlock;
80    #[inline(always)]
81    fn deref(&self) -> &Self::Target {
82        unsafe { &*AUX_ADI4::ptr() }
83    }
84}
85#[doc = "Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic)"]
86#[cfg(feature = "aux_adi4")]
87pub mod aux_adi4;
88#[doc = "Always On (AON) Battery And Temperature MONitor (BATMON) residing in the AON domain Note: This module only supports 32 bit Read/Write access from MCU."]
89pub struct AON_BATMON {
90    _marker: PhantomData<*const ()>,
91}
92unsafe impl Send for AON_BATMON {}
93#[cfg(feature = "aon_batmon")]
94impl AON_BATMON {
95    #[doc = r"Returns a pointer to the register block"]
96    #[inline(always)]
97    pub const fn ptr() -> *const aon_batmon::RegisterBlock {
98        0x4009_5000 as *const _
99    }
100}
101#[cfg(feature = "aon_batmon")]
102impl Deref for AON_BATMON {
103    type Target = aon_batmon::RegisterBlock;
104    #[inline(always)]
105    fn deref(&self) -> &Self::Target {
106        unsafe { &*AON_BATMON::ptr() }
107    }
108}
109#[doc = "Always On (AON) Battery And Temperature MONitor (BATMON) residing in the AON domain Note: This module only supports 32 bit Read/Write access from MCU."]
110#[cfg(feature = "aon_batmon")]
111pub mod aon_batmon;
112#[doc = "This module configures the event fabric located in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU"]
113pub struct AON_EVENT {
114    _marker: PhantomData<*const ()>,
115}
116unsafe impl Send for AON_EVENT {}
117#[cfg(feature = "aon_event")]
118impl AON_EVENT {
119    #[doc = r"Returns a pointer to the register block"]
120    #[inline(always)]
121    pub const fn ptr() -> *const aon_event::RegisterBlock {
122        0x4009_3000 as *const _
123    }
124}
125#[cfg(feature = "aon_event")]
126impl Deref for AON_EVENT {
127    type Target = aon_event::RegisterBlock;
128    #[inline(always)]
129    fn deref(&self) -> &Self::Target {
130        unsafe { &*AON_EVENT::ptr() }
131    }
132}
133#[doc = "This module configures the event fabric located in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU"]
134#[cfg(feature = "aon_event")]
135pub mod aon_event;
136#[doc = "Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain. Note: This module only supports 32 bit Read/Write access from MCU."]
137pub struct AON_IOC {
138    _marker: PhantomData<*const ()>,
139}
140unsafe impl Send for AON_IOC {}
141#[cfg(feature = "aon_ioc")]
142impl AON_IOC {
143    #[doc = r"Returns a pointer to the register block"]
144    #[inline(always)]
145    pub const fn ptr() -> *const aon_ioc::RegisterBlock {
146        0x4009_4000 as *const _
147    }
148}
149#[cfg(feature = "aon_ioc")]
150impl Deref for AON_IOC {
151    type Target = aon_ioc::RegisterBlock;
152    #[inline(always)]
153    fn deref(&self) -> &Self::Target {
154        unsafe { &*AON_IOC::ptr() }
155    }
156}
157#[doc = "Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain. Note: This module only supports 32 bit Read/Write access from MCU."]
158#[cfg(feature = "aon_ioc")]
159pub mod aon_ioc;
160#[doc = "This component control the Power Management controller residing in the AON domain. Note: This module is only supporting 32 bit Read Write access from MCU"]
161pub struct AON_PMCTL {
162    _marker: PhantomData<*const ()>,
163}
164unsafe impl Send for AON_PMCTL {}
165#[cfg(feature = "aon_pmctl")]
166impl AON_PMCTL {
167    #[doc = r"Returns a pointer to the register block"]
168    #[inline(always)]
169    pub const fn ptr() -> *const aon_pmctl::RegisterBlock {
170        0x4009_0000 as *const _
171    }
172}
173#[cfg(feature = "aon_pmctl")]
174impl Deref for AON_PMCTL {
175    type Target = aon_pmctl::RegisterBlock;
176    #[inline(always)]
177    fn deref(&self) -> &Self::Target {
178        unsafe { &*AON_PMCTL::ptr() }
179    }
180}
181#[doc = "This component control the Power Management controller residing in the AON domain. Note: This module is only supporting 32 bit Read Write access from MCU"]
182#[cfg(feature = "aon_pmctl")]
183pub mod aon_pmctl;
184#[doc = "This component control the Real Time Clock residing in AON Note: This module is only supporting 32 bit ReadWrite access."]
185pub struct AON_RTC {
186    _marker: PhantomData<*const ()>,
187}
188unsafe impl Send for AON_RTC {}
189#[cfg(feature = "aon_rtc")]
190impl AON_RTC {
191    #[doc = r"Returns a pointer to the register block"]
192    #[inline(always)]
193    pub const fn ptr() -> *const aon_rtc::RegisterBlock {
194        0x4009_2000 as *const _
195    }
196}
197#[cfg(feature = "aon_rtc")]
198impl Deref for AON_RTC {
199    type Target = aon_rtc::RegisterBlock;
200    #[inline(always)]
201    fn deref(&self) -> &Self::Target {
202        unsafe { &*AON_RTC::ptr() }
203    }
204}
205#[doc = "This component control the Real Time Clock residing in AON Note: This module is only supporting 32 bit ReadWrite access."]
206#[cfg(feature = "aon_rtc")]
207pub mod aon_rtc;
208#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n]
209does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
210pub struct AUX_AIODIO0 {
211    _marker: PhantomData<*const ()>,
212}
213unsafe impl Send for AUX_AIODIO0 {}
214#[cfg(feature = "aux_aiodio0")]
215impl AUX_AIODIO0 {
216    #[doc = r"Returns a pointer to the register block"]
217    #[inline(always)]
218    pub const fn ptr() -> *const aux_aiodio0::RegisterBlock {
219        0x400c_c000 as *const _
220    }
221}
222#[cfg(feature = "aux_aiodio0")]
223impl Deref for AUX_AIODIO0 {
224    type Target = aux_aiodio0::RegisterBlock;
225    #[inline(always)]
226    fn deref(&self) -> &Self::Target {
227        unsafe { &*AUX_AIODIO0::ptr() }
228    }
229}
230#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\]
231does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
232#[cfg(feature = "aux_aiodio0")]
233pub mod aux_aiodio0;
234#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n]
235does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
236pub struct AUX_AIODIO1 {
237    _marker: PhantomData<*const ()>,
238}
239unsafe impl Send for AUX_AIODIO1 {}
240#[cfg(feature = "aux_aiodio1")]
241impl AUX_AIODIO1 {
242    #[doc = r"Returns a pointer to the register block"]
243    #[inline(always)]
244    pub const fn ptr() -> *const aux_aiodio1::RegisterBlock {
245        0x400c_d000 as *const _
246    }
247}
248#[cfg(feature = "aux_aiodio1")]
249impl Deref for AUX_AIODIO1 {
250    type Target = aux_aiodio1::RegisterBlock;
251    #[inline(always)]
252    fn deref(&self) -> &Self::Target {
253        unsafe { &*AUX_AIODIO1::ptr() }
254    }
255}
256#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\]
257does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
258#[cfg(feature = "aux_aiodio1")]
259pub mod aux_aiodio1;
260#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n]
261does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
262pub struct AUX_AIODIO2 {
263    _marker: PhantomData<*const ()>,
264}
265unsafe impl Send for AUX_AIODIO2 {}
266#[cfg(feature = "aux_aiodio2")]
267impl AUX_AIODIO2 {
268    #[doc = r"Returns a pointer to the register block"]
269    #[inline(always)]
270    pub const fn ptr() -> *const aux_aiodio2::RegisterBlock {
271        0x400c_e000 as *const _
272    }
273}
274#[cfg(feature = "aux_aiodio2")]
275impl Deref for AUX_AIODIO2 {
276    type Target = aux_aiodio2::RegisterBlock;
277    #[inline(always)]
278    fn deref(&self) -> &Self::Target {
279        unsafe { &*AUX_AIODIO2::ptr() }
280    }
281}
282#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\]
283does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
284#[cfg(feature = "aux_aiodio2")]
285pub mod aux_aiodio2;
286#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n]
287does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
288pub struct AUX_AIODIO3 {
289    _marker: PhantomData<*const ()>,
290}
291unsafe impl Send for AUX_AIODIO3 {}
292#[cfg(feature = "aux_aiodio3")]
293impl AUX_AIODIO3 {
294    #[doc = r"Returns a pointer to the register block"]
295    #[inline(always)]
296    pub const fn ptr() -> *const aux_aiodio3::RegisterBlock {
297        0x400c_f000 as *const _
298    }
299}
300#[cfg(feature = "aux_aiodio3")]
301impl Deref for AUX_AIODIO3 {
302    type Target = aux_aiodio3::RegisterBlock;
303    #[inline(always)]
304    fn deref(&self) -> &Self::Target {
305        unsafe { &*AUX_AIODIO3::ptr() }
306    }
307}
308#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\]
309does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
310#[cfg(feature = "aux_aiodio3")]
311pub mod aux_aiodio3;
312#[doc = "AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets AUX_SCE, UDMA0, and system CPU: -Trigger ADC sample and conversion process. - Write ADC samples to FIFO. - Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information. - Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes. To use: - ADC : AUX_SCE must request active operational mode with AON_PMCTL:AUXSCECLK.SRC set to SCLK_HFDIV2. There are no requirements for system CPU. - ISRC : AUX_SCE must request active operational mode. There are no requirements for system CPU. - DAC : AUX_SCE must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to SCE_RATE as long as DAC state machine generates the sample clock. System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information."]
313pub struct AUX_ANAIF {
314    _marker: PhantomData<*const ()>,
315}
316unsafe impl Send for AUX_ANAIF {}
317#[cfg(feature = "aux_anaif")]
318impl AUX_ANAIF {
319    #[doc = r"Returns a pointer to the register block"]
320    #[inline(always)]
321    pub const fn ptr() -> *const aux_anaif::RegisterBlock {
322        0x400c_9000 as *const _
323    }
324}
325#[cfg(feature = "aux_anaif")]
326impl Deref for AUX_ANAIF {
327    type Target = aux_anaif::RegisterBlock;
328    #[inline(always)]
329    fn deref(&self) -> &Self::Target {
330        unsafe { &*AUX_ANAIF::ptr() }
331    }
332}
333#[doc = "AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets AUX_SCE, UDMA0, and system CPU: -Trigger ADC sample and conversion process. - Write ADC samples to FIFO. - Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information. - Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes. To use: - ADC : AUX_SCE must request active operational mode with AON_PMCTL:AUXSCECLK.SRC set to SCLK_HFDIV2. There are no requirements for system CPU. - ISRC : AUX_SCE must request active operational mode. There are no requirements for system CPU. - DAC : AUX_SCE must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to SCE_RATE as long as DAC state machine generates the sample clock. System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information."]
334#[cfg(feature = "aux_anaif")]
335pub mod aux_anaif;
336#[doc = "AUX Event Controller (AUX_EVCTL) assembles events originating from: - AUX submodules, including ADC and comparators. - AUXIO. - EVENT. - AON_PMCTL. - AON_RTC. - AON_BATMON. into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized. The subscribers to the synchronous event bus are AUX_TIMER01, AUX_SCE and AUX_EVCTL. The subscribers to the asynchronous event bus are AUX_TIMER2, AUX_ANAIF, AUX_TDC and AUX_SYSIF. AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT, as well as to AUX_SCE. AUX_SCE can poll event status registers and combine certain instructions like WEV0, WEV1 with one or two configurable events. The latter saves power when execution must stall until a condition is met."]
337pub struct AUX_EVCTL {
338    _marker: PhantomData<*const ()>,
339}
340unsafe impl Send for AUX_EVCTL {}
341#[cfg(feature = "aux_evctl")]
342impl AUX_EVCTL {
343    #[doc = r"Returns a pointer to the register block"]
344    #[inline(always)]
345    pub const fn ptr() -> *const aux_evctl::RegisterBlock {
346        0x400c_5000 as *const _
347    }
348}
349#[cfg(feature = "aux_evctl")]
350impl Deref for AUX_EVCTL {
351    type Target = aux_evctl::RegisterBlock;
352    #[inline(always)]
353    fn deref(&self) -> &Self::Target {
354        unsafe { &*AUX_EVCTL::ptr() }
355    }
356}
357#[doc = "AUX Event Controller (AUX_EVCTL) assembles events originating from: - AUX submodules, including ADC and comparators. - AUXIO. - EVENT. - AON_PMCTL. - AON_RTC. - AON_BATMON. into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized. The subscribers to the synchronous event bus are AUX_TIMER01, AUX_SCE and AUX_EVCTL. The subscribers to the asynchronous event bus are AUX_TIMER2, AUX_ANAIF, AUX_TDC and AUX_SYSIF. AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT, as well as to AUX_SCE. AUX_SCE can poll event status registers and combine certain instructions like WEV0, WEV1 with one or two configurable events. The latter saves power when execution must stall until a condition is met."]
358#[cfg(feature = "aux_evctl")]
359pub mod aux_evctl;
360#[doc = "The AUX Multiply-Accumulate (AUX_MAC) peripheral enables AUX_SCE with power-efficient and flexible mathematical operations: - 2's complement signed and unsigned sequential multiplication (MUL) with optional accumulation of the result (MAC). - 16 or 32-bit 2's complement signed and unsigned addition of configurable term and accumulator (ADD). - Results of ADD, MUL and MAC operations are always stored in the accumulator (ACC). Software can easily: - Access arbitrary 16-bit slice of the 40-bit accumulator. - Find the number of leading zero or sign bits. - Perform shift operations on the accumulator. AUX_SCE must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to SCE_RATE to access and use AUX_MAC. System CPU must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to BUS_RATE to access and use AUX_MAC. This guarantees constant execution times for ADD, MUL, and MAC operations. The ADD operation requires a single peripheral clock cycle to finish. MUL and MAC operations require four peripheral clock periods to finish. An unfinished ADD, MUL, or MAC operation stalls register access to this peripheral. AUX_SCE becomes clock gated if it encounters a bus stall. Software can use this to reduce power consumption during back to back accesses. Only full word access is supported by the peripheral. An attempt to write a single byte will have no effect."]
361pub struct AUX_MAC {
362    _marker: PhantomData<*const ()>,
363}
364unsafe impl Send for AUX_MAC {}
365#[cfg(feature = "aux_mac")]
366impl AUX_MAC {
367    #[doc = r"Returns a pointer to the register block"]
368    #[inline(always)]
369    pub const fn ptr() -> *const aux_mac::RegisterBlock {
370        0x400c_2000 as *const _
371    }
372}
373#[cfg(feature = "aux_mac")]
374impl Deref for AUX_MAC {
375    type Target = aux_mac::RegisterBlock;
376    #[inline(always)]
377    fn deref(&self) -> &Self::Target {
378        unsafe { &*AUX_MAC::ptr() }
379    }
380}
381#[doc = "The AUX Multiply-Accumulate (AUX_MAC) peripheral enables AUX_SCE with power-efficient and flexible mathematical operations: - 2's complement signed and unsigned sequential multiplication (MUL) with optional accumulation of the result (MAC). - 16 or 32-bit 2's complement signed and unsigned addition of configurable term and accumulator (ADD). - Results of ADD, MUL and MAC operations are always stored in the accumulator (ACC). Software can easily: - Access arbitrary 16-bit slice of the 40-bit accumulator. - Find the number of leading zero or sign bits. - Perform shift operations on the accumulator. AUX_SCE must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to SCE_RATE to access and use AUX_MAC. System CPU must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to BUS_RATE to access and use AUX_MAC. This guarantees constant execution times for ADD, MUL, and MAC operations. The ADD operation requires a single peripheral clock cycle to finish. MUL and MAC operations require four peripheral clock periods to finish. An unfinished ADD, MUL, or MAC operation stalls register access to this peripheral. AUX_SCE becomes clock gated if it encounters a bus stall. Software can use this to reduce power consumption during back to back accesses. Only full word access is supported by the peripheral. An attempt to write a single byte will have no effect."]
382#[cfg(feature = "aux_mac")]
383pub mod aux_mac;
384#[doc = "AUX Sensor Control Engine (AUX_SCE) is a RISC-style microprocessor with separate fetch and execution cycles. It is optimized for low power and simple operations. AUX_SCE code and data segments are stored in AUX_RAM. AON_PMCTL:AUXSCECLK sets the operational frequency."]
385pub struct AUX_SCE {
386    _marker: PhantomData<*const ()>,
387}
388unsafe impl Send for AUX_SCE {}
389#[cfg(feature = "aux_sce")]
390impl AUX_SCE {
391    #[doc = r"Returns a pointer to the register block"]
392    #[inline(always)]
393    pub const fn ptr() -> *const aux_sce::RegisterBlock {
394        0x400e_1000 as *const _
395    }
396}
397#[cfg(feature = "aux_sce")]
398impl Deref for AUX_SCE {
399    type Target = aux_sce::RegisterBlock;
400    #[inline(always)]
401    fn deref(&self) -> &Self::Target {
402        unsafe { &*AUX_SCE::ptr() }
403    }
404}
405#[doc = "AUX Sensor Control Engine (AUX_SCE) is a RISC-style microprocessor with separate fetch and execution cycles. It is optimized for low power and simple operations. AUX_SCE code and data segments are stored in AUX_RAM. AON_PMCTL:AUXSCECLK sets the operational frequency."]
406#[cfg(feature = "aux_sce")]
407pub mod aux_sce;
408#[doc = "AUX Semaphore (AUX_SMPH) provides hardware means to share modules in AUX safely between CPUs based on resource ownership. AUX_SMPH operates at AUX bus rate."]
409pub struct AUX_SMPH {
410    _marker: PhantomData<*const ()>,
411}
412unsafe impl Send for AUX_SMPH {}
413#[cfg(feature = "aux_smph")]
414impl AUX_SMPH {
415    #[doc = r"Returns a pointer to the register block"]
416    #[inline(always)]
417    pub const fn ptr() -> *const aux_smph::RegisterBlock {
418        0x400c_8000 as *const _
419    }
420}
421#[cfg(feature = "aux_smph")]
422impl Deref for AUX_SMPH {
423    type Target = aux_smph::RegisterBlock;
424    #[inline(always)]
425    fn deref(&self) -> &Self::Target {
426        unsafe { &*AUX_SMPH::ptr() }
427    }
428}
429#[doc = "AUX Semaphore (AUX_SMPH) provides hardware means to share modules in AUX safely between CPUs based on resource ownership. AUX_SMPH operates at AUX bus rate."]
430#[cfg(feature = "aux_smph")]
431pub mod aux_smph;
432#[doc = "The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication. It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete. Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus. AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers. AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency. AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission."]
433pub struct AUX_SPIM {
434    _marker: PhantomData<*const ()>,
435}
436unsafe impl Send for AUX_SPIM {}
437#[cfg(feature = "aux_spim")]
438impl AUX_SPIM {
439    #[doc = r"Returns a pointer to the register block"]
440    #[inline(always)]
441    pub const fn ptr() -> *const aux_spim::RegisterBlock {
442        0x400c_1000 as *const _
443    }
444}
445#[cfg(feature = "aux_spim")]
446impl Deref for AUX_SPIM {
447    type Target = aux_spim::RegisterBlock;
448    #[inline(always)]
449    fn deref(&self) -> &Self::Target {
450        unsafe { &*AUX_SPIM::ptr() }
451    }
452}
453#[doc = "The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication. It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete. Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus. AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers. AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency. AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission."]
454#[cfg(feature = "aux_spim")]
455pub mod aux_spim;
456#[doc = "AUX System Interface (AUX_SYSIF) is responsible for: - system resource requests, such as power supply, clock and, wakeup requests. - configuration of AUX peripheral operational rates for AUX_SPIM, AUX_MAC, AUX_ANAIF DAC state machine and AUX_TIMER01. - configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3. - configuration of AUX_SCE wakeup vectors that trigger AUX_SCE execution from sleep. Peripheral operational rate for AUX modules mentioned above can either be: - SCE rate, which is configured in AON_PMCTL:AUXSCECLK. - AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active. AUX_SYSIF also interfaces AON_RTC and AON_BATMON to enable read access to data and sub-second increment control of AON_RTC."]
457pub struct AUX_SYSIF {
458    _marker: PhantomData<*const ()>,
459}
460unsafe impl Send for AUX_SYSIF {}
461#[cfg(feature = "aux_sysif")]
462impl AUX_SYSIF {
463    #[doc = r"Returns a pointer to the register block"]
464    #[inline(always)]
465    pub const fn ptr() -> *const aux_sysif::RegisterBlock {
466        0x400c_6000 as *const _
467    }
468}
469#[cfg(feature = "aux_sysif")]
470impl Deref for AUX_SYSIF {
471    type Target = aux_sysif::RegisterBlock;
472    #[inline(always)]
473    fn deref(&self) -> &Self::Target {
474        unsafe { &*AUX_SYSIF::ptr() }
475    }
476}
477#[doc = "AUX System Interface (AUX_SYSIF) is responsible for: - system resource requests, such as power supply, clock and, wakeup requests. - configuration of AUX peripheral operational rates for AUX_SPIM, AUX_MAC, AUX_ANAIF DAC state machine and AUX_TIMER01. - configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3. - configuration of AUX_SCE wakeup vectors that trigger AUX_SCE execution from sleep. Peripheral operational rate for AUX modules mentioned above can either be: - SCE rate, which is configured in AON_PMCTL:AUXSCECLK. - AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active. AUX_SYSIF also interfaces AON_RTC and AON_BATMON to enable read access to data and sub-second increment control of AON_RTC."]
478#[cfg(feature = "aux_sysif")]
479pub mod aux_sysif;
480#[doc = "AUX Time To Digital Converter (AUX_TDC) is used to measure the time between two events with high resolution. AUX_TDC consists of a state machine that operates at AUX bus rate and an asynchronous fast-counter which is clocked by the TDC clock. DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL configures TDC clock source. The fast-counter counts on both edges of the TDC clock to double the resolution. See the Technical Reference Manual for event timing requirements."]
481pub struct AUX_TDC {
482    _marker: PhantomData<*const ()>,
483}
484unsafe impl Send for AUX_TDC {}
485#[cfg(feature = "aux_tdc")]
486impl AUX_TDC {
487    #[doc = r"Returns a pointer to the register block"]
488    #[inline(always)]
489    pub const fn ptr() -> *const aux_tdc::RegisterBlock {
490        0x400c_4000 as *const _
491    }
492}
493#[cfg(feature = "aux_tdc")]
494impl Deref for AUX_TDC {
495    type Target = aux_tdc::RegisterBlock;
496    #[inline(always)]
497    fn deref(&self) -> &Self::Target {
498        unsafe { &*AUX_TDC::ptr() }
499    }
500}
501#[doc = "AUX Time To Digital Converter (AUX_TDC) is used to measure the time between two events with high resolution. AUX_TDC consists of a state machine that operates at AUX bus rate and an asynchronous fast-counter which is clocked by the TDC clock. DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL configures TDC clock source. The fast-counter counts on both edges of the TDC clock to double the resolution. See the Technical Reference Manual for event timing requirements."]
502#[cfg(feature = "aux_tdc")]
503pub mod aux_tdc;
504#[doc = "AUX Timer 0 and AUX Timer 1 (AUX_TIMER01) are two 16-bit timers capable of generating one event each: - AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV. - AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV. The events are described in T0TARGET and T1TARGET. Subscribers to the AUX event bus can use these events to sequence and trigger actions. AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the peripheral clock frequency used by the prescaler, timer, and event logic to SCE or AUX bus rate. To use AUX_TIMER01: - AUX_SCE must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to SCE_RATE. - System CPU must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to BUS_RATE. - The timers must only subscribe to events updated at the peripheral clock frequency or lower. Unexpected execution behavior can result if software does not obey these rules."]
505pub struct AUX_TIMER01 {
506    _marker: PhantomData<*const ()>,
507}
508unsafe impl Send for AUX_TIMER01 {}
509#[cfg(feature = "aux_timer01")]
510impl AUX_TIMER01 {
511    #[doc = r"Returns a pointer to the register block"]
512    #[inline(always)]
513    pub const fn ptr() -> *const aux_timer01::RegisterBlock {
514        0x400c_7000 as *const _
515    }
516}
517#[cfg(feature = "aux_timer01")]
518impl Deref for AUX_TIMER01 {
519    type Target = aux_timer01::RegisterBlock;
520    #[inline(always)]
521    fn deref(&self) -> &Self::Target {
522        unsafe { &*AUX_TIMER01::ptr() }
523    }
524}
525#[doc = "AUX Timer 0 and AUX Timer 1 (AUX_TIMER01) are two 16-bit timers capable of generating one event each: - AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV. - AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV. The events are described in T0TARGET and T1TARGET. Subscribers to the AUX event bus can use these events to sequence and trigger actions. AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the peripheral clock frequency used by the prescaler, timer, and event logic to SCE or AUX bus rate. To use AUX_TIMER01: - AUX_SCE must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to SCE_RATE. - System CPU must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to BUS_RATE. - The timers must only subscribe to events updated at the peripheral clock frequency or lower. Unexpected execution behavior can result if software does not obey these rules."]
526#[cfg(feature = "aux_timer01")]
527pub mod aux_timer01;
528#[doc = "AUX Timer2 (AUX_TIMER2) offers flexible: - generation of waveforms and events. - capture of signal period and duty cycle. - generation of single clock pulse. It consists of a: - 16-bit counter. - 4 capture compare channels. - 4 event outputs, which are mapped to AUX event bus, see EVCTL. Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer."]
529pub struct AUX_TIMER2 {
530    _marker: PhantomData<*const ()>,
531}
532unsafe impl Send for AUX_TIMER2 {}
533#[cfg(feature = "aux_timer2")]
534impl AUX_TIMER2 {
535    #[doc = r"Returns a pointer to the register block"]
536    #[inline(always)]
537    pub const fn ptr() -> *const aux_timer2::RegisterBlock {
538        0x400c_3000 as *const _
539    }
540}
541#[cfg(feature = "aux_timer2")]
542impl Deref for AUX_TIMER2 {
543    type Target = aux_timer2::RegisterBlock;
544    #[inline(always)]
545    fn deref(&self) -> &Self::Target {
546        unsafe { &*AUX_TIMER2::ptr() }
547    }
548}
549#[doc = "AUX Timer2 (AUX_TIMER2) offers flexible: - generation of waveforms and events. - capture of signal period and duty cycle. - generation of single clock pulse. It consists of a: - 16-bit counter. - 4 capture compare channels. - 4 event outputs, which are mapped to AUX event bus, see EVCTL. Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer."]
550#[cfg(feature = "aux_timer2")]
551pub mod aux_timer2;
552#[doc = "Customer configuration area (CCFG)"]
553pub struct CCFG {
554    _marker: PhantomData<*const ()>,
555}
556unsafe impl Send for CCFG {}
557#[cfg(feature = "ccfg")]
558impl CCFG {
559    #[doc = r"Returns a pointer to the register block"]
560    #[inline(always)]
561    pub const fn ptr() -> *const ccfg::RegisterBlock {
562        0x5000_3000 as *const _
563    }
564}
565#[cfg(feature = "ccfg")]
566impl Deref for CCFG {
567    type Target = ccfg::RegisterBlock;
568    #[inline(always)]
569    fn deref(&self) -> &Self::Target {
570        unsafe { &*CCFG::ptr() }
571    }
572}
573#[doc = "Customer configuration area (CCFG)"]
574#[cfg(feature = "ccfg")]
575pub mod ccfg;
576#[doc = "Cortex-M's Data watchpoint and Trace (DWT)"]
577pub struct CPU_DWT {
578    _marker: PhantomData<*const ()>,
579}
580unsafe impl Send for CPU_DWT {}
581#[cfg(feature = "cpu_dwt")]
582impl CPU_DWT {
583    #[doc = r"Returns a pointer to the register block"]
584    #[inline(always)]
585    pub const fn ptr() -> *const cpu_dwt::RegisterBlock {
586        0xe000_1000 as *const _
587    }
588}
589#[cfg(feature = "cpu_dwt")]
590impl Deref for CPU_DWT {
591    type Target = cpu_dwt::RegisterBlock;
592    #[inline(always)]
593    fn deref(&self) -> &Self::Target {
594        unsafe { &*CPU_DWT::ptr() }
595    }
596}
597#[doc = "Cortex-M's Data watchpoint and Trace (DWT)"]
598#[cfg(feature = "cpu_dwt")]
599pub mod cpu_dwt;
600#[doc = "Cortex-M's Flash Patch and Breakpoint (FPB)"]
601pub struct CPU_FPB {
602    _marker: PhantomData<*const ()>,
603}
604unsafe impl Send for CPU_FPB {}
605#[cfg(feature = "cpu_fpb")]
606impl CPU_FPB {
607    #[doc = r"Returns a pointer to the register block"]
608    #[inline(always)]
609    pub const fn ptr() -> *const cpu_fpb::RegisterBlock {
610        0xe000_2000 as *const _
611    }
612}
613#[cfg(feature = "cpu_fpb")]
614impl Deref for CPU_FPB {
615    type Target = cpu_fpb::RegisterBlock;
616    #[inline(always)]
617    fn deref(&self) -> &Self::Target {
618        unsafe { &*CPU_FPB::ptr() }
619    }
620}
621#[doc = "Cortex-M's Flash Patch and Breakpoint (FPB)"]
622#[cfg(feature = "cpu_fpb")]
623pub mod cpu_fpb;
624#[doc = "Cortex-M's Instrumentation Trace Macrocell (ITM)"]
625pub struct CPU_ITM {
626    _marker: PhantomData<*const ()>,
627}
628unsafe impl Send for CPU_ITM {}
629#[cfg(feature = "cpu_itm")]
630impl CPU_ITM {
631    #[doc = r"Returns a pointer to the register block"]
632    #[inline(always)]
633    pub const fn ptr() -> *const cpu_itm::RegisterBlock {
634        0xe000_0000 as *const _
635    }
636}
637#[cfg(feature = "cpu_itm")]
638impl Deref for CPU_ITM {
639    type Target = cpu_itm::RegisterBlock;
640    #[inline(always)]
641    fn deref(&self) -> &Self::Target {
642        unsafe { &*CPU_ITM::ptr() }
643    }
644}
645#[doc = "Cortex-M's Instrumentation Trace Macrocell (ITM)"]
646#[cfg(feature = "cpu_itm")]
647pub mod cpu_itm;
648#[doc = "Cortex-M's System Control Space (SCS)"]
649pub struct CPU_SCS {
650    _marker: PhantomData<*const ()>,
651}
652unsafe impl Send for CPU_SCS {}
653#[cfg(feature = "cpu_scs")]
654impl CPU_SCS {
655    #[doc = r"Returns a pointer to the register block"]
656    #[inline(always)]
657    pub const fn ptr() -> *const cpu_scs::RegisterBlock {
658        0xe000_e000 as *const _
659    }
660}
661#[cfg(feature = "cpu_scs")]
662impl Deref for CPU_SCS {
663    type Target = cpu_scs::RegisterBlock;
664    #[inline(always)]
665    fn deref(&self) -> &Self::Target {
666        unsafe { &*CPU_SCS::ptr() }
667    }
668}
669#[doc = "Cortex-M's System Control Space (SCS)"]
670#[cfg(feature = "cpu_scs")]
671pub mod cpu_scs;
672#[doc = "Cortex-M's TI proprietary registers"]
673pub struct CPU_TIPROP {
674    _marker: PhantomData<*const ()>,
675}
676unsafe impl Send for CPU_TIPROP {}
677#[cfg(feature = "cpu_tiprop")]
678impl CPU_TIPROP {
679    #[doc = r"Returns a pointer to the register block"]
680    #[inline(always)]
681    pub const fn ptr() -> *const cpu_tiprop::RegisterBlock {
682        0xe00f_e000 as *const _
683    }
684}
685#[cfg(feature = "cpu_tiprop")]
686impl Deref for CPU_TIPROP {
687    type Target = cpu_tiprop::RegisterBlock;
688    #[inline(always)]
689    fn deref(&self) -> &Self::Target {
690        unsafe { &*CPU_TIPROP::ptr() }
691    }
692}
693#[doc = "Cortex-M's TI proprietary registers"]
694#[cfg(feature = "cpu_tiprop")]
695pub mod cpu_tiprop;
696#[doc = "Cortex-M's Trace Port Interface Unit (TPIU)"]
697pub struct CPU_TPIU {
698    _marker: PhantomData<*const ()>,
699}
700unsafe impl Send for CPU_TPIU {}
701#[cfg(feature = "cpu_tpiu")]
702impl CPU_TPIU {
703    #[doc = r"Returns a pointer to the register block"]
704    #[inline(always)]
705    pub const fn ptr() -> *const cpu_tpiu::RegisterBlock {
706        0xe004_0000 as *const _
707    }
708}
709#[cfg(feature = "cpu_tpiu")]
710impl Deref for CPU_TPIU {
711    type Target = cpu_tpiu::RegisterBlock;
712    #[inline(always)]
713    fn deref(&self) -> &Self::Target {
714        unsafe { &*CPU_TPIU::ptr() }
715    }
716}
717#[doc = "Cortex-M's Trace Port Interface Unit (TPIU)"]
718#[cfg(feature = "cpu_tpiu")]
719pub mod cpu_tpiu;
720#[doc = "DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage."]
721pub struct CRYPTO {
722    _marker: PhantomData<*const ()>,
723}
724unsafe impl Send for CRYPTO {}
725#[cfg(feature = "crypto")]
726impl CRYPTO {
727    #[doc = r"Returns a pointer to the register block"]
728    #[inline(always)]
729    pub const fn ptr() -> *const crypto::RegisterBlock {
730        0x4002_4000 as *const _
731    }
732}
733#[cfg(feature = "crypto")]
734impl Deref for CRYPTO {
735    type Target = crypto::RegisterBlock;
736    #[inline(always)]
737    fn deref(&self) -> &Self::Target {
738        unsafe { &*CRYPTO::ptr() }
739    }
740}
741#[doc = "DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage."]
742#[cfg(feature = "crypto")]
743pub mod crypto;
744#[doc = "This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated."]
745pub struct AUX_DDI0_OSC {
746    _marker: PhantomData<*const ()>,
747}
748unsafe impl Send for AUX_DDI0_OSC {}
749#[cfg(feature = "aux_ddi0_osc")]
750impl AUX_DDI0_OSC {
751    #[doc = r"Returns a pointer to the register block"]
752    #[inline(always)]
753    pub const fn ptr() -> *const aux_ddi0_osc::RegisterBlock {
754        0x400c_a000 as *const _
755    }
756}
757#[cfg(feature = "aux_ddi0_osc")]
758impl Deref for AUX_DDI0_OSC {
759    type Target = aux_ddi0_osc::RegisterBlock;
760    #[inline(always)]
761    fn deref(&self) -> &Self::Target {
762        unsafe { &*AUX_DDI0_OSC::ptr() }
763    }
764}
765#[doc = "This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated."]
766#[cfg(feature = "aux_ddi0_osc")]
767pub mod aux_ddi0_osc;
768#[doc = "Event Fabric Component Definition"]
769pub struct EVENT {
770    _marker: PhantomData<*const ()>,
771}
772unsafe impl Send for EVENT {}
773#[cfg(feature = "event")]
774impl EVENT {
775    #[doc = r"Returns a pointer to the register block"]
776    #[inline(always)]
777    pub const fn ptr() -> *const event::RegisterBlock {
778        0x4008_3000 as *const _
779    }
780}
781#[cfg(feature = "event")]
782impl Deref for EVENT {
783    type Target = event::RegisterBlock;
784    #[inline(always)]
785    fn deref(&self) -> &Self::Target {
786        unsafe { &*EVENT::ptr() }
787    }
788}
789#[doc = "Event Fabric Component Definition"]
790#[cfg(feature = "event")]
791pub mod event;
792#[doc = "Factory configuration area (FCFG1)"]
793pub struct FCFG1 {
794    _marker: PhantomData<*const ()>,
795}
796unsafe impl Send for FCFG1 {}
797#[cfg(feature = "fcfg1")]
798impl FCFG1 {
799    #[doc = r"Returns a pointer to the register block"]
800    #[inline(always)]
801    pub const fn ptr() -> *const fcfg1::RegisterBlock {
802        0x5000_1000 as *const _
803    }
804}
805#[cfg(feature = "fcfg1")]
806impl Deref for FCFG1 {
807    type Target = fcfg1::RegisterBlock;
808    #[inline(always)]
809    fn deref(&self) -> &Self::Target {
810        unsafe { &*FCFG1::ptr() }
811    }
812}
813#[doc = "Factory configuration area (FCFG1)"]
814#[cfg(feature = "fcfg1")]
815pub mod fcfg1;
816#[doc = "Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM."]
817pub struct FLASH {
818    _marker: PhantomData<*const ()>,
819}
820unsafe impl Send for FLASH {}
821#[cfg(feature = "flash")]
822impl FLASH {
823    #[doc = r"Returns a pointer to the register block"]
824    #[inline(always)]
825    pub const fn ptr() -> *const flash::RegisterBlock {
826        0x4003_0000 as *const _
827    }
828}
829#[cfg(feature = "flash")]
830impl Deref for FLASH {
831    type Target = flash::RegisterBlock;
832    #[inline(always)]
833    fn deref(&self) -> &Self::Target {
834        unsafe { &*FLASH::ptr() }
835    }
836}
837#[doc = "Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM."]
838#[cfg(feature = "flash")]
839pub mod flash;
840#[doc = "MCU GPIO - I/F for controlling and reading IO status and IO event status"]
841pub struct GPIO {
842    _marker: PhantomData<*const ()>,
843}
844unsafe impl Send for GPIO {}
845#[cfg(feature = "gpio")]
846impl GPIO {
847    #[doc = r"Returns a pointer to the register block"]
848    #[inline(always)]
849    pub const fn ptr() -> *const gpio::RegisterBlock {
850        0x4002_2000 as *const _
851    }
852}
853#[cfg(feature = "gpio")]
854impl Deref for GPIO {
855    type Target = gpio::RegisterBlock;
856    #[inline(always)]
857    fn deref(&self) -> &Self::Target {
858        unsafe { &*GPIO::ptr() }
859    }
860}
861#[doc = "MCU GPIO - I/F for controlling and reading IO status and IO event status"]
862#[cfg(feature = "gpio")]
863pub mod gpio;
864#[doc = "General Purpose Timer."]
865pub struct GPT0 {
866    _marker: PhantomData<*const ()>,
867}
868unsafe impl Send for GPT0 {}
869#[cfg(feature = "gpt0")]
870impl GPT0 {
871    #[doc = r"Returns a pointer to the register block"]
872    #[inline(always)]
873    pub const fn ptr() -> *const gpt0::RegisterBlock {
874        0x4001_0000 as *const _
875    }
876}
877#[cfg(feature = "gpt0")]
878impl Deref for GPT0 {
879    type Target = gpt0::RegisterBlock;
880    #[inline(always)]
881    fn deref(&self) -> &Self::Target {
882        unsafe { &*GPT0::ptr() }
883    }
884}
885#[doc = "General Purpose Timer."]
886#[cfg(feature = "gpt0")]
887pub mod gpt0;
888#[doc = "General Purpose Timer."]
889pub struct GPT1 {
890    _marker: PhantomData<*const ()>,
891}
892unsafe impl Send for GPT1 {}
893#[cfg(feature = "gpt1")]
894impl GPT1 {
895    #[doc = r"Returns a pointer to the register block"]
896    #[inline(always)]
897    pub const fn ptr() -> *const gpt1::RegisterBlock {
898        0x4001_1000 as *const _
899    }
900}
901#[cfg(feature = "gpt1")]
902impl Deref for GPT1 {
903    type Target = gpt1::RegisterBlock;
904    #[inline(always)]
905    fn deref(&self) -> &Self::Target {
906        unsafe { &*GPT1::ptr() }
907    }
908}
909#[doc = "General Purpose Timer."]
910#[cfg(feature = "gpt1")]
911pub mod gpt1;
912#[doc = "General Purpose Timer."]
913pub struct GPT2 {
914    _marker: PhantomData<*const ()>,
915}
916unsafe impl Send for GPT2 {}
917#[cfg(feature = "gpt2")]
918impl GPT2 {
919    #[doc = r"Returns a pointer to the register block"]
920    #[inline(always)]
921    pub const fn ptr() -> *const gpt2::RegisterBlock {
922        0x4001_2000 as *const _
923    }
924}
925#[cfg(feature = "gpt2")]
926impl Deref for GPT2 {
927    type Target = gpt2::RegisterBlock;
928    #[inline(always)]
929    fn deref(&self) -> &Self::Target {
930        unsafe { &*GPT2::ptr() }
931    }
932}
933#[doc = "General Purpose Timer."]
934#[cfg(feature = "gpt2")]
935pub mod gpt2;
936#[doc = "General Purpose Timer."]
937pub struct GPT3 {
938    _marker: PhantomData<*const ()>,
939}
940unsafe impl Send for GPT3 {}
941#[cfg(feature = "gpt3")]
942impl GPT3 {
943    #[doc = r"Returns a pointer to the register block"]
944    #[inline(always)]
945    pub const fn ptr() -> *const gpt3::RegisterBlock {
946        0x4001_3000 as *const _
947    }
948}
949#[cfg(feature = "gpt3")]
950impl Deref for GPT3 {
951    type Target = gpt3::RegisterBlock;
952    #[inline(always)]
953    fn deref(&self) -> &Self::Target {
954        unsafe { &*GPT3::ptr() }
955    }
956}
957#[doc = "General Purpose Timer."]
958#[cfg(feature = "gpt3")]
959pub mod gpt3;
960#[doc = "I2CMaster/Slave Serial Controler"]
961pub struct I2C0 {
962    _marker: PhantomData<*const ()>,
963}
964unsafe impl Send for I2C0 {}
965#[cfg(feature = "i2c0")]
966impl I2C0 {
967    #[doc = r"Returns a pointer to the register block"]
968    #[inline(always)]
969    pub const fn ptr() -> *const i2c0::RegisterBlock {
970        0x4000_2000 as *const _
971    }
972}
973#[cfg(feature = "i2c0")]
974impl Deref for I2C0 {
975    type Target = i2c0::RegisterBlock;
976    #[inline(always)]
977    fn deref(&self) -> &Self::Target {
978        unsafe { &*I2C0::ptr() }
979    }
980}
981#[doc = "I2CMaster/Slave Serial Controler"]
982#[cfg(feature = "i2c0")]
983pub mod i2c0;
984#[doc = "I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP"]
985pub struct I2S0 {
986    _marker: PhantomData<*const ()>,
987}
988unsafe impl Send for I2S0 {}
989#[cfg(feature = "i2s0")]
990impl I2S0 {
991    #[doc = r"Returns a pointer to the register block"]
992    #[inline(always)]
993    pub const fn ptr() -> *const i2s0::RegisterBlock {
994        0x4002_1000 as *const _
995    }
996}
997#[cfg(feature = "i2s0")]
998impl Deref for I2S0 {
999    type Target = i2s0::RegisterBlock;
1000    #[inline(always)]
1001    fn deref(&self) -> &Self::Target {
1002        unsafe { &*I2S0::ptr() }
1003    }
1004}
1005#[doc = "I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP"]
1006#[cfg(feature = "i2s0")]
1007pub mod i2s0;
1008#[doc = "IO Controller (IOC) - configures all the DIOs and resides in the MCU domain."]
1009pub struct IOC {
1010    _marker: PhantomData<*const ()>,
1011}
1012unsafe impl Send for IOC {}
1013#[cfg(feature = "ioc")]
1014impl IOC {
1015    #[doc = r"Returns a pointer to the register block"]
1016    #[inline(always)]
1017    pub const fn ptr() -> *const ioc::RegisterBlock {
1018        0x4008_1000 as *const _
1019    }
1020}
1021#[cfg(feature = "ioc")]
1022impl Deref for IOC {
1023    type Target = ioc::RegisterBlock;
1024    #[inline(always)]
1025    fn deref(&self) -> &Self::Target {
1026        unsafe { &*IOC::ptr() }
1027    }
1028}
1029#[doc = "IO Controller (IOC) - configures all the DIOs and resides in the MCU domain."]
1030#[cfg(feature = "ioc")]
1031pub mod ioc;
1032#[doc = "Integrated module which combines the Public Key Acceleration module, optional True Random Gnerator, optional interrupt controller and a standard bus interface"]
1033pub struct PKA {
1034    _marker: PhantomData<*const ()>,
1035}
1036unsafe impl Send for PKA {}
1037#[cfg(feature = "pka")]
1038impl PKA {
1039    #[doc = r"Returns a pointer to the register block"]
1040    #[inline(always)]
1041    pub const fn ptr() -> *const pka::RegisterBlock {
1042        0x4002_5000 as *const _
1043    }
1044}
1045#[cfg(feature = "pka")]
1046impl Deref for PKA {
1047    type Target = pka::RegisterBlock;
1048    #[inline(always)]
1049    fn deref(&self) -> &Self::Target {
1050        unsafe { &*PKA::ptr() }
1051    }
1052}
1053#[doc = "Integrated module which combines the Public Key Acceleration module, optional True Random Gnerator, optional interrupt controller and a standard bus interface"]
1054#[cfg(feature = "pka")]
1055pub mod pka;
1056#[doc = "Integrated module which includes the PKA K"]
1057pub struct PKA_INT {
1058    _marker: PhantomData<*const ()>,
1059}
1060unsafe impl Send for PKA_INT {}
1061#[cfg(feature = "pka_int")]
1062impl PKA_INT {
1063    #[doc = r"Returns a pointer to the register block"]
1064    #[inline(always)]
1065    pub const fn ptr() -> *const pka_int::RegisterBlock {
1066        0x4002_7000 as *const _
1067    }
1068}
1069#[cfg(feature = "pka_int")]
1070impl Deref for PKA_INT {
1071    type Target = pka_int::RegisterBlock;
1072    #[inline(always)]
1073    fn deref(&self) -> &Self::Target {
1074        unsafe { &*PKA_INT::ptr() }
1075    }
1076}
1077#[doc = "Integrated module which includes the PKA K"]
1078#[cfg(feature = "pka_int")]
1079pub mod pka_int;
1080#[doc = "Power, Reset and Clock Management"]
1081pub struct PRCM {
1082    _marker: PhantomData<*const ()>,
1083}
1084unsafe impl Send for PRCM {}
1085#[cfg(feature = "prcm")]
1086impl PRCM {
1087    #[doc = r"Returns a pointer to the register block"]
1088    #[inline(always)]
1089    pub const fn ptr() -> *const prcm::RegisterBlock {
1090        0x4008_2000 as *const _
1091    }
1092}
1093#[cfg(feature = "prcm")]
1094impl Deref for PRCM {
1095    type Target = prcm::RegisterBlock;
1096    #[inline(always)]
1097    fn deref(&self) -> &Self::Target {
1098        unsafe { &*PRCM::ptr() }
1099    }
1100}
1101#[doc = "Power, Reset and Clock Management"]
1102#[cfg(feature = "prcm")]
1103pub mod prcm;
1104#[doc = "RF core doorbell The doorbell module is the main user interface to the radio sub-system. It contains the registers used for both submitting commands to the radio, and for configuring radio interrupts from the RF core."]
1105pub struct RFC_DBELL {
1106    _marker: PhantomData<*const ()>,
1107}
1108unsafe impl Send for RFC_DBELL {}
1109#[cfg(feature = "rfc_dbell")]
1110impl RFC_DBELL {
1111    #[doc = r"Returns a pointer to the register block"]
1112    #[inline(always)]
1113    pub const fn ptr() -> *const rfc_dbell::RegisterBlock {
1114        0x4004_1000 as *const _
1115    }
1116}
1117#[cfg(feature = "rfc_dbell")]
1118impl Deref for RFC_DBELL {
1119    type Target = rfc_dbell::RegisterBlock;
1120    #[inline(always)]
1121    fn deref(&self) -> &Self::Target {
1122        unsafe { &*RFC_DBELL::ptr() }
1123    }
1124}
1125#[doc = "RF core doorbell The doorbell module is the main user interface to the radio sub-system. It contains the registers used for both submitting commands to the radio, and for configuring radio interrupts from the RF core."]
1126#[cfg(feature = "rfc_dbell")]
1127pub mod rfc_dbell;
1128#[doc = "RF core power management This module contains clock control for all RF core sub-modules."]
1129pub struct RFC_PWR {
1130    _marker: PhantomData<*const ()>,
1131}
1132unsafe impl Send for RFC_PWR {}
1133#[cfg(feature = "rfc_pwr")]
1134impl RFC_PWR {
1135    #[doc = r"Returns a pointer to the register block"]
1136    #[inline(always)]
1137    pub const fn ptr() -> *const rfc_pwr::RegisterBlock {
1138        0x4004_0000 as *const _
1139    }
1140}
1141#[cfg(feature = "rfc_pwr")]
1142impl Deref for RFC_PWR {
1143    type Target = rfc_pwr::RegisterBlock;
1144    #[inline(always)]
1145    fn deref(&self) -> &Self::Target {
1146        unsafe { &*RFC_PWR::ptr() }
1147    }
1148}
1149#[doc = "RF core power management This module contains clock control for all RF core sub-modules."]
1150#[cfg(feature = "rfc_pwr")]
1151pub mod rfc_pwr;
1152#[doc = "RF core radio timer"]
1153pub struct RFC_RAT {
1154    _marker: PhantomData<*const ()>,
1155}
1156unsafe impl Send for RFC_RAT {}
1157#[cfg(feature = "rfc_rat")]
1158impl RFC_RAT {
1159    #[doc = r"Returns a pointer to the register block"]
1160    #[inline(always)]
1161    pub const fn ptr() -> *const rfc_rat::RegisterBlock {
1162        0x4004_3000 as *const _
1163    }
1164}
1165#[cfg(feature = "rfc_rat")]
1166impl Deref for RFC_RAT {
1167    type Target = rfc_rat::RegisterBlock;
1168    #[inline(always)]
1169    fn deref(&self) -> &Self::Target {
1170        unsafe { &*RFC_RAT::ptr() }
1171    }
1172}
1173#[doc = "RF core radio timer"]
1174#[cfg(feature = "rfc_rat")]
1175pub mod rfc_rat;
1176#[doc = "MCU Semaphore Module This module provides 32 binary semaphores. The state of a binary semaphore is either taken or available. A semaphore does not implement any ownership attribute. Still, a semaphore can be used to handle mutual exclusion scenarios."]
1177pub struct SMPH {
1178    _marker: PhantomData<*const ()>,
1179}
1180unsafe impl Send for SMPH {}
1181#[cfg(feature = "smph")]
1182impl SMPH {
1183    #[doc = r"Returns a pointer to the register block"]
1184    #[inline(always)]
1185    pub const fn ptr() -> *const smph::RegisterBlock {
1186        0x4008_4000 as *const _
1187    }
1188}
1189#[cfg(feature = "smph")]
1190impl Deref for SMPH {
1191    type Target = smph::RegisterBlock;
1192    #[inline(always)]
1193    fn deref(&self) -> &Self::Target {
1194        unsafe { &*SMPH::ptr() }
1195    }
1196}
1197#[doc = "MCU Semaphore Module This module provides 32 binary semaphores. The state of a binary semaphore is either taken or available. A semaphore does not implement any ownership attribute. Still, a semaphore can be used to handle mutual exclusion scenarios."]
1198#[cfg(feature = "smph")]
1199pub mod smph;
1200#[doc = "General Purpose RAM"]
1201pub struct SRAM_MMR {
1202    _marker: PhantomData<*const ()>,
1203}
1204unsafe impl Send for SRAM_MMR {}
1205#[cfg(feature = "sram_mmr")]
1206impl SRAM_MMR {
1207    #[doc = r"Returns a pointer to the register block"]
1208    #[inline(always)]
1209    pub const fn ptr() -> *const sram_mmr::RegisterBlock {
1210        0x4003_5000 as *const _
1211    }
1212}
1213#[cfg(feature = "sram_mmr")]
1214impl Deref for SRAM_MMR {
1215    type Target = sram_mmr::RegisterBlock;
1216    #[inline(always)]
1217    fn deref(&self) -> &Self::Target {
1218        unsafe { &*SRAM_MMR::ptr() }
1219    }
1220}
1221#[doc = "General Purpose RAM"]
1222#[cfg(feature = "sram_mmr")]
1223pub mod sram_mmr;
1224#[doc = "Synchronous Serial Interface with master and slave capabilities"]
1225pub struct SSI0 {
1226    _marker: PhantomData<*const ()>,
1227}
1228unsafe impl Send for SSI0 {}
1229#[cfg(feature = "ssi0")]
1230impl SSI0 {
1231    #[doc = r"Returns a pointer to the register block"]
1232    #[inline(always)]
1233    pub const fn ptr() -> *const ssi0::RegisterBlock {
1234        0x4000_0000 as *const _
1235    }
1236}
1237#[cfg(feature = "ssi0")]
1238impl Deref for SSI0 {
1239    type Target = ssi0::RegisterBlock;
1240    #[inline(always)]
1241    fn deref(&self) -> &Self::Target {
1242        unsafe { &*SSI0::ptr() }
1243    }
1244}
1245#[doc = "Synchronous Serial Interface with master and slave capabilities"]
1246#[cfg(feature = "ssi0")]
1247pub mod ssi0;
1248#[doc = "Synchronous Serial Interface with master and slave capabilities"]
1249pub struct SSI1 {
1250    _marker: PhantomData<*const ()>,
1251}
1252unsafe impl Send for SSI1 {}
1253#[cfg(feature = "ssi1")]
1254impl SSI1 {
1255    #[doc = r"Returns a pointer to the register block"]
1256    #[inline(always)]
1257    pub const fn ptr() -> *const ssi1::RegisterBlock {
1258        0x4000_8000 as *const _
1259    }
1260}
1261#[cfg(feature = "ssi1")]
1262impl Deref for SSI1 {
1263    type Target = ssi1::RegisterBlock;
1264    #[inline(always)]
1265    fn deref(&self) -> &Self::Target {
1266        unsafe { &*SSI1::ptr() }
1267    }
1268}
1269#[doc = "Synchronous Serial Interface with master and slave capabilities"]
1270#[cfg(feature = "ssi1")]
1271pub mod ssi1;
1272#[doc = "True Random Number Generator"]
1273pub struct TRNG {
1274    _marker: PhantomData<*const ()>,
1275}
1276unsafe impl Send for TRNG {}
1277#[cfg(feature = "trng")]
1278impl TRNG {
1279    #[doc = r"Returns a pointer to the register block"]
1280    #[inline(always)]
1281    pub const fn ptr() -> *const trng::RegisterBlock {
1282        0x4002_8000 as *const _
1283    }
1284}
1285#[cfg(feature = "trng")]
1286impl Deref for TRNG {
1287    type Target = trng::RegisterBlock;
1288    #[inline(always)]
1289    fn deref(&self) -> &Self::Target {
1290        unsafe { &*TRNG::ptr() }
1291    }
1292}
1293#[doc = "True Random Number Generator"]
1294#[cfg(feature = "trng")]
1295pub mod trng;
1296#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1297pub struct UART0 {
1298    _marker: PhantomData<*const ()>,
1299}
1300unsafe impl Send for UART0 {}
1301#[cfg(feature = "uart0")]
1302impl UART0 {
1303    #[doc = r"Returns a pointer to the register block"]
1304    #[inline(always)]
1305    pub const fn ptr() -> *const uart0::RegisterBlock {
1306        0x4000_1000 as *const _
1307    }
1308}
1309#[cfg(feature = "uart0")]
1310impl Deref for UART0 {
1311    type Target = uart0::RegisterBlock;
1312    #[inline(always)]
1313    fn deref(&self) -> &Self::Target {
1314        unsafe { &*UART0::ptr() }
1315    }
1316}
1317#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1318#[cfg(feature = "uart0")]
1319pub mod uart0;
1320#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1321pub struct UART1 {
1322    _marker: PhantomData<*const ()>,
1323}
1324unsafe impl Send for UART1 {}
1325#[cfg(feature = "uart1")]
1326impl UART1 {
1327    #[doc = r"Returns a pointer to the register block"]
1328    #[inline(always)]
1329    pub const fn ptr() -> *const uart1::RegisterBlock {
1330        0x4000_b000 as *const _
1331    }
1332}
1333#[cfg(feature = "uart1")]
1334impl Deref for UART1 {
1335    type Target = uart1::RegisterBlock;
1336    #[inline(always)]
1337    fn deref(&self) -> &Self::Target {
1338        unsafe { &*UART1::ptr() }
1339    }
1340}
1341#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1342#[cfg(feature = "uart1")]
1343pub mod uart1;
1344#[doc = "ARM Micro Direct Memory Access Controller"]
1345pub struct UDMA0 {
1346    _marker: PhantomData<*const ()>,
1347}
1348unsafe impl Send for UDMA0 {}
1349#[cfg(feature = "udma0")]
1350impl UDMA0 {
1351    #[doc = r"Returns a pointer to the register block"]
1352    #[inline(always)]
1353    pub const fn ptr() -> *const udma0::RegisterBlock {
1354        0x4002_0000 as *const _
1355    }
1356}
1357#[cfg(feature = "udma0")]
1358impl Deref for UDMA0 {
1359    type Target = udma0::RegisterBlock;
1360    #[inline(always)]
1361    fn deref(&self) -> &Self::Target {
1362        unsafe { &*UDMA0::ptr() }
1363    }
1364}
1365#[doc = "ARM Micro Direct Memory Access Controller"]
1366#[cfg(feature = "udma0")]
1367pub mod udma0;
1368#[doc = "Versatile Instruction Memory System Controls memory access to the Flash and encapsulates the following instruction memories: - Boot ROM - Cache / GPRAM"]
1369pub struct VIMS {
1370    _marker: PhantomData<*const ()>,
1371}
1372unsafe impl Send for VIMS {}
1373#[cfg(feature = "vims")]
1374impl VIMS {
1375    #[doc = r"Returns a pointer to the register block"]
1376    #[inline(always)]
1377    pub const fn ptr() -> *const vims::RegisterBlock {
1378        0x4003_4000 as *const _
1379    }
1380}
1381#[cfg(feature = "vims")]
1382impl Deref for VIMS {
1383    type Target = vims::RegisterBlock;
1384    #[inline(always)]
1385    fn deref(&self) -> &Self::Target {
1386        unsafe { &*VIMS::ptr() }
1387    }
1388}
1389#[doc = "Versatile Instruction Memory System Controls memory access to the Flash and encapsulates the following instruction memories: - Boot ROM - Cache / GPRAM"]
1390#[cfg(feature = "vims")]
1391pub mod vims;
1392#[doc = "Watchdog Timer"]
1393pub struct WDT {
1394    _marker: PhantomData<*const ()>,
1395}
1396unsafe impl Send for WDT {}
1397#[cfg(feature = "wdt")]
1398impl WDT {
1399    #[doc = r"Returns a pointer to the register block"]
1400    #[inline(always)]
1401    pub const fn ptr() -> *const wdt::RegisterBlock {
1402        0x4008_0000 as *const _
1403    }
1404}
1405#[cfg(feature = "wdt")]
1406impl Deref for WDT {
1407    type Target = wdt::RegisterBlock;
1408    #[inline(always)]
1409    fn deref(&self) -> &Self::Target {
1410        unsafe { &*WDT::ptr() }
1411    }
1412}
1413#[doc = "Watchdog Timer"]
1414#[cfg(feature = "wdt")]
1415pub mod wdt;
1416#[no_mangle]
1417static mut DEVICE_PERIPHERALS: bool = false;
1418#[doc = r"All the peripherals"]
1419#[allow(non_snake_case)]
1420pub struct Peripherals {
1421    #[doc = "AUX_ADI4"]
1422    pub AUX_ADI4: AUX_ADI4,
1423    #[doc = "AON_BATMON"]
1424    pub AON_BATMON: AON_BATMON,
1425    #[doc = "AON_EVENT"]
1426    pub AON_EVENT: AON_EVENT,
1427    #[doc = "AON_IOC"]
1428    pub AON_IOC: AON_IOC,
1429    #[doc = "AON_PMCTL"]
1430    pub AON_PMCTL: AON_PMCTL,
1431    #[doc = "AON_RTC"]
1432    pub AON_RTC: AON_RTC,
1433    #[doc = "AUX_AIODIO0"]
1434    pub AUX_AIODIO0: AUX_AIODIO0,
1435    #[doc = "AUX_AIODIO1"]
1436    pub AUX_AIODIO1: AUX_AIODIO1,
1437    #[doc = "AUX_AIODIO2"]
1438    pub AUX_AIODIO2: AUX_AIODIO2,
1439    #[doc = "AUX_AIODIO3"]
1440    pub AUX_AIODIO3: AUX_AIODIO3,
1441    #[doc = "AUX_ANAIF"]
1442    pub AUX_ANAIF: AUX_ANAIF,
1443    #[doc = "AUX_EVCTL"]
1444    pub AUX_EVCTL: AUX_EVCTL,
1445    #[doc = "AUX_MAC"]
1446    pub AUX_MAC: AUX_MAC,
1447    #[doc = "AUX_SCE"]
1448    pub AUX_SCE: AUX_SCE,
1449    #[doc = "AUX_SMPH"]
1450    pub AUX_SMPH: AUX_SMPH,
1451    #[doc = "AUX_SPIM"]
1452    pub AUX_SPIM: AUX_SPIM,
1453    #[doc = "AUX_SYSIF"]
1454    pub AUX_SYSIF: AUX_SYSIF,
1455    #[doc = "AUX_TDC"]
1456    pub AUX_TDC: AUX_TDC,
1457    #[doc = "AUX_TIMER01"]
1458    pub AUX_TIMER01: AUX_TIMER01,
1459    #[doc = "AUX_TIMER2"]
1460    pub AUX_TIMER2: AUX_TIMER2,
1461    #[doc = "CCFG"]
1462    pub CCFG: CCFG,
1463    #[doc = "CPU_DWT"]
1464    pub CPU_DWT: CPU_DWT,
1465    #[doc = "CPU_FPB"]
1466    pub CPU_FPB: CPU_FPB,
1467    #[doc = "CPU_ITM"]
1468    pub CPU_ITM: CPU_ITM,
1469    #[doc = "CPU_SCS"]
1470    pub CPU_SCS: CPU_SCS,
1471    #[doc = "CPU_TIPROP"]
1472    pub CPU_TIPROP: CPU_TIPROP,
1473    #[doc = "CPU_TPIU"]
1474    pub CPU_TPIU: CPU_TPIU,
1475    #[doc = "CRYPTO"]
1476    pub CRYPTO: CRYPTO,
1477    #[doc = "AUX_DDI0_OSC"]
1478    pub AUX_DDI0_OSC: AUX_DDI0_OSC,
1479    #[doc = "EVENT"]
1480    pub EVENT: EVENT,
1481    #[doc = "FCFG1"]
1482    pub FCFG1: FCFG1,
1483    #[doc = "FLASH"]
1484    pub FLASH: FLASH,
1485    #[doc = "GPIO"]
1486    pub GPIO: GPIO,
1487    #[doc = "GPT0"]
1488    pub GPT0: GPT0,
1489    #[doc = "GPT1"]
1490    pub GPT1: GPT1,
1491    #[doc = "GPT2"]
1492    pub GPT2: GPT2,
1493    #[doc = "GPT3"]
1494    pub GPT3: GPT3,
1495    #[doc = "I2C0"]
1496    pub I2C0: I2C0,
1497    #[doc = "I2S0"]
1498    pub I2S0: I2S0,
1499    #[doc = "IOC"]
1500    pub IOC: IOC,
1501    #[doc = "PKA"]
1502    pub PKA: PKA,
1503    #[doc = "PKA_INT"]
1504    pub PKA_INT: PKA_INT,
1505    #[doc = "PRCM"]
1506    pub PRCM: PRCM,
1507    #[doc = "RFC_DBELL"]
1508    pub RFC_DBELL: RFC_DBELL,
1509    #[doc = "RFC_PWR"]
1510    pub RFC_PWR: RFC_PWR,
1511    #[doc = "RFC_RAT"]
1512    pub RFC_RAT: RFC_RAT,
1513    #[doc = "SMPH"]
1514    pub SMPH: SMPH,
1515    #[doc = "SRAM_MMR"]
1516    pub SRAM_MMR: SRAM_MMR,
1517    #[doc = "SSI0"]
1518    pub SSI0: SSI0,
1519    #[doc = "SSI1"]
1520    pub SSI1: SSI1,
1521    #[doc = "TRNG"]
1522    pub TRNG: TRNG,
1523    #[doc = "UART0"]
1524    pub UART0: UART0,
1525    #[doc = "UART1"]
1526    pub UART1: UART1,
1527    #[doc = "UDMA0"]
1528    pub UDMA0: UDMA0,
1529    #[doc = "VIMS"]
1530    pub VIMS: VIMS,
1531    #[doc = "WDT"]
1532    pub WDT: WDT,
1533}
1534impl Peripherals {
1535    #[doc = r"Returns all the peripherals *once*"]
1536    #[inline]
1537    pub fn take() -> Option<Self> {
1538        cortex_m::interrupt::free(|_| {
1539            if unsafe { DEVICE_PERIPHERALS } {
1540                None
1541            } else {
1542                Some(unsafe { Peripherals::steal() })
1543            }
1544        })
1545    }
1546    #[doc = r"Unchecked version of `Peripherals::take`"]
1547    #[inline]
1548    pub unsafe fn steal() -> Self {
1549        DEVICE_PERIPHERALS = true;
1550        Peripherals {
1551            AUX_ADI4: AUX_ADI4 {
1552                _marker: PhantomData,
1553            },
1554            AON_BATMON: AON_BATMON {
1555                _marker: PhantomData,
1556            },
1557            AON_EVENT: AON_EVENT {
1558                _marker: PhantomData,
1559            },
1560            AON_IOC: AON_IOC {
1561                _marker: PhantomData,
1562            },
1563            AON_PMCTL: AON_PMCTL {
1564                _marker: PhantomData,
1565            },
1566            AON_RTC: AON_RTC {
1567                _marker: PhantomData,
1568            },
1569            AUX_AIODIO0: AUX_AIODIO0 {
1570                _marker: PhantomData,
1571            },
1572            AUX_AIODIO1: AUX_AIODIO1 {
1573                _marker: PhantomData,
1574            },
1575            AUX_AIODIO2: AUX_AIODIO2 {
1576                _marker: PhantomData,
1577            },
1578            AUX_AIODIO3: AUX_AIODIO3 {
1579                _marker: PhantomData,
1580            },
1581            AUX_ANAIF: AUX_ANAIF {
1582                _marker: PhantomData,
1583            },
1584            AUX_EVCTL: AUX_EVCTL {
1585                _marker: PhantomData,
1586            },
1587            AUX_MAC: AUX_MAC {
1588                _marker: PhantomData,
1589            },
1590            AUX_SCE: AUX_SCE {
1591                _marker: PhantomData,
1592            },
1593            AUX_SMPH: AUX_SMPH {
1594                _marker: PhantomData,
1595            },
1596            AUX_SPIM: AUX_SPIM {
1597                _marker: PhantomData,
1598            },
1599            AUX_SYSIF: AUX_SYSIF {
1600                _marker: PhantomData,
1601            },
1602            AUX_TDC: AUX_TDC {
1603                _marker: PhantomData,
1604            },
1605            AUX_TIMER01: AUX_TIMER01 {
1606                _marker: PhantomData,
1607            },
1608            AUX_TIMER2: AUX_TIMER2 {
1609                _marker: PhantomData,
1610            },
1611            CCFG: CCFG {
1612                _marker: PhantomData,
1613            },
1614            CPU_DWT: CPU_DWT {
1615                _marker: PhantomData,
1616            },
1617            CPU_FPB: CPU_FPB {
1618                _marker: PhantomData,
1619            },
1620            CPU_ITM: CPU_ITM {
1621                _marker: PhantomData,
1622            },
1623            CPU_SCS: CPU_SCS {
1624                _marker: PhantomData,
1625            },
1626            CPU_TIPROP: CPU_TIPROP {
1627                _marker: PhantomData,
1628            },
1629            CPU_TPIU: CPU_TPIU {
1630                _marker: PhantomData,
1631            },
1632            CRYPTO: CRYPTO {
1633                _marker: PhantomData,
1634            },
1635            AUX_DDI0_OSC: AUX_DDI0_OSC {
1636                _marker: PhantomData,
1637            },
1638            EVENT: EVENT {
1639                _marker: PhantomData,
1640            },
1641            FCFG1: FCFG1 {
1642                _marker: PhantomData,
1643            },
1644            FLASH: FLASH {
1645                _marker: PhantomData,
1646            },
1647            GPIO: GPIO {
1648                _marker: PhantomData,
1649            },
1650            GPT0: GPT0 {
1651                _marker: PhantomData,
1652            },
1653            GPT1: GPT1 {
1654                _marker: PhantomData,
1655            },
1656            GPT2: GPT2 {
1657                _marker: PhantomData,
1658            },
1659            GPT3: GPT3 {
1660                _marker: PhantomData,
1661            },
1662            I2C0: I2C0 {
1663                _marker: PhantomData,
1664            },
1665            I2S0: I2S0 {
1666                _marker: PhantomData,
1667            },
1668            IOC: IOC {
1669                _marker: PhantomData,
1670            },
1671            PKA: PKA {
1672                _marker: PhantomData,
1673            },
1674            PKA_INT: PKA_INT {
1675                _marker: PhantomData,
1676            },
1677            PRCM: PRCM {
1678                _marker: PhantomData,
1679            },
1680            RFC_DBELL: RFC_DBELL {
1681                _marker: PhantomData,
1682            },
1683            RFC_PWR: RFC_PWR {
1684                _marker: PhantomData,
1685            },
1686            RFC_RAT: RFC_RAT {
1687                _marker: PhantomData,
1688            },
1689            SMPH: SMPH {
1690                _marker: PhantomData,
1691            },
1692            SRAM_MMR: SRAM_MMR {
1693                _marker: PhantomData,
1694            },
1695            SSI0: SSI0 {
1696                _marker: PhantomData,
1697            },
1698            SSI1: SSI1 {
1699                _marker: PhantomData,
1700            },
1701            TRNG: TRNG {
1702                _marker: PhantomData,
1703            },
1704            UART0: UART0 {
1705                _marker: PhantomData,
1706            },
1707            UART1: UART1 {
1708                _marker: PhantomData,
1709            },
1710            UDMA0: UDMA0 {
1711                _marker: PhantomData,
1712            },
1713            VIMS: VIMS {
1714                _marker: PhantomData,
1715            },
1716            WDT: WDT {
1717                _marker: PhantomData,
1718            },
1719        }
1720    }
1721}
cc13x2/lib.rs

cc13x2/
lib.rs
