cc13x2_cc26x2_pac/uart0/
mis.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::MIS {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct RESERVED12R {
47    bits: u32,
48}
49impl RESERVED12R {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u32 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct EOTMISR {
58    bits: bool,
59}
60impl EOTMISR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct OEMISR {
79    bits: bool,
80}
81impl OEMISR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bit(&self) -> bool {
85        self.bits
86    }
87    #[doc = r" Returns `true` if the bit is clear (0)"]
88    #[inline]
89    pub fn bit_is_clear(&self) -> bool {
90        !self.bit()
91    }
92    #[doc = r" Returns `true` if the bit is set (1)"]
93    #[inline]
94    pub fn bit_is_set(&self) -> bool {
95        self.bit()
96    }
97}
98#[doc = r" Value of the field"]
99pub struct BEMISR {
100    bits: bool,
101}
102impl BEMISR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bit(&self) -> bool {
106        self.bits
107    }
108    #[doc = r" Returns `true` if the bit is clear (0)"]
109    #[inline]
110    pub fn bit_is_clear(&self) -> bool {
111        !self.bit()
112    }
113    #[doc = r" Returns `true` if the bit is set (1)"]
114    #[inline]
115    pub fn bit_is_set(&self) -> bool {
116        self.bit()
117    }
118}
119#[doc = r" Value of the field"]
120pub struct PEMISR {
121    bits: bool,
122}
123impl PEMISR {
124    #[doc = r" Value of the field as raw bits"]
125    #[inline]
126    pub fn bit(&self) -> bool {
127        self.bits
128    }
129    #[doc = r" Returns `true` if the bit is clear (0)"]
130    #[inline]
131    pub fn bit_is_clear(&self) -> bool {
132        !self.bit()
133    }
134    #[doc = r" Returns `true` if the bit is set (1)"]
135    #[inline]
136    pub fn bit_is_set(&self) -> bool {
137        self.bit()
138    }
139}
140#[doc = r" Value of the field"]
141pub struct FEMISR {
142    bits: bool,
143}
144impl FEMISR {
145    #[doc = r" Value of the field as raw bits"]
146    #[inline]
147    pub fn bit(&self) -> bool {
148        self.bits
149    }
150    #[doc = r" Returns `true` if the bit is clear (0)"]
151    #[inline]
152    pub fn bit_is_clear(&self) -> bool {
153        !self.bit()
154    }
155    #[doc = r" Returns `true` if the bit is set (1)"]
156    #[inline]
157    pub fn bit_is_set(&self) -> bool {
158        self.bit()
159    }
160}
161#[doc = r" Value of the field"]
162pub struct RTMISR {
163    bits: bool,
164}
165impl RTMISR {
166    #[doc = r" Value of the field as raw bits"]
167    #[inline]
168    pub fn bit(&self) -> bool {
169        self.bits
170    }
171    #[doc = r" Returns `true` if the bit is clear (0)"]
172    #[inline]
173    pub fn bit_is_clear(&self) -> bool {
174        !self.bit()
175    }
176    #[doc = r" Returns `true` if the bit is set (1)"]
177    #[inline]
178    pub fn bit_is_set(&self) -> bool {
179        self.bit()
180    }
181}
182#[doc = r" Value of the field"]
183pub struct TXMISR {
184    bits: bool,
185}
186impl TXMISR {
187    #[doc = r" Value of the field as raw bits"]
188    #[inline]
189    pub fn bit(&self) -> bool {
190        self.bits
191    }
192    #[doc = r" Returns `true` if the bit is clear (0)"]
193    #[inline]
194    pub fn bit_is_clear(&self) -> bool {
195        !self.bit()
196    }
197    #[doc = r" Returns `true` if the bit is set (1)"]
198    #[inline]
199    pub fn bit_is_set(&self) -> bool {
200        self.bit()
201    }
202}
203#[doc = r" Value of the field"]
204pub struct RXMISR {
205    bits: bool,
206}
207impl RXMISR {
208    #[doc = r" Value of the field as raw bits"]
209    #[inline]
210    pub fn bit(&self) -> bool {
211        self.bits
212    }
213    #[doc = r" Returns `true` if the bit is clear (0)"]
214    #[inline]
215    pub fn bit_is_clear(&self) -> bool {
216        !self.bit()
217    }
218    #[doc = r" Returns `true` if the bit is set (1)"]
219    #[inline]
220    pub fn bit_is_set(&self) -> bool {
221        self.bit()
222    }
223}
224#[doc = r" Value of the field"]
225pub struct RESERVED2R {
226    bits: u8,
227}
228impl RESERVED2R {
229    #[doc = r" Value of the field as raw bits"]
230    #[inline]
231    pub fn bits(&self) -> u8 {
232        self.bits
233    }
234}
235#[doc = r" Value of the field"]
236pub struct CTSMMISR {
237    bits: bool,
238}
239impl CTSMMISR {
240    #[doc = r" Value of the field as raw bits"]
241    #[inline]
242    pub fn bit(&self) -> bool {
243        self.bits
244    }
245    #[doc = r" Returns `true` if the bit is clear (0)"]
246    #[inline]
247    pub fn bit_is_clear(&self) -> bool {
248        !self.bit()
249    }
250    #[doc = r" Returns `true` if the bit is set (1)"]
251    #[inline]
252    pub fn bit_is_set(&self) -> bool {
253        self.bit()
254    }
255}
256#[doc = r" Value of the field"]
257pub struct RESERVED0R {
258    bits: bool,
259}
260impl RESERVED0R {
261    #[doc = r" Value of the field as raw bits"]
262    #[inline]
263    pub fn bit(&self) -> bool {
264        self.bits
265    }
266    #[doc = r" Returns `true` if the bit is clear (0)"]
267    #[inline]
268    pub fn bit_is_clear(&self) -> bool {
269        !self.bit()
270    }
271    #[doc = r" Returns `true` if the bit is set (1)"]
272    #[inline]
273    pub fn bit_is_set(&self) -> bool {
274        self.bit()
275    }
276}
277#[doc = r" Proxy"]
278pub struct _RESERVED12W<'a> {
279    w: &'a mut W,
280}
281impl<'a> _RESERVED12W<'a> {
282    #[doc = r" Writes raw bits to the field"]
283    #[inline]
284    pub unsafe fn bits(self, value: u32) -> &'a mut W {
285        const MASK: u32 = 1048575;
286        const OFFSET: u8 = 12;
287        self.w.bits &= !((MASK as u32) << OFFSET);
288        self.w.bits |= ((value & MASK) as u32) << OFFSET;
289        self.w
290    }
291}
292#[doc = r" Proxy"]
293pub struct _EOTMISW<'a> {
294    w: &'a mut W,
295}
296impl<'a> _EOTMISW<'a> {
297    #[doc = r" Sets the field bit"]
298    pub fn set_bit(self) -> &'a mut W {
299        self.bit(true)
300    }
301    #[doc = r" Clears the field bit"]
302    pub fn clear_bit(self) -> &'a mut W {
303        self.bit(false)
304    }
305    #[doc = r" Writes raw bits to the field"]
306    #[inline]
307    pub fn bit(self, value: bool) -> &'a mut W {
308        const MASK: bool = true;
309        const OFFSET: u8 = 11;
310        self.w.bits &= !((MASK as u32) << OFFSET);
311        self.w.bits |= ((value & MASK) as u32) << OFFSET;
312        self.w
313    }
314}
315#[doc = r" Proxy"]
316pub struct _OEMISW<'a> {
317    w: &'a mut W,
318}
319impl<'a> _OEMISW<'a> {
320    #[doc = r" Sets the field bit"]
321    pub fn set_bit(self) -> &'a mut W {
322        self.bit(true)
323    }
324    #[doc = r" Clears the field bit"]
325    pub fn clear_bit(self) -> &'a mut W {
326        self.bit(false)
327    }
328    #[doc = r" Writes raw bits to the field"]
329    #[inline]
330    pub fn bit(self, value: bool) -> &'a mut W {
331        const MASK: bool = true;
332        const OFFSET: u8 = 10;
333        self.w.bits &= !((MASK as u32) << OFFSET);
334        self.w.bits |= ((value & MASK) as u32) << OFFSET;
335        self.w
336    }
337}
338#[doc = r" Proxy"]
339pub struct _BEMISW<'a> {
340    w: &'a mut W,
341}
342impl<'a> _BEMISW<'a> {
343    #[doc = r" Sets the field bit"]
344    pub fn set_bit(self) -> &'a mut W {
345        self.bit(true)
346    }
347    #[doc = r" Clears the field bit"]
348    pub fn clear_bit(self) -> &'a mut W {
349        self.bit(false)
350    }
351    #[doc = r" Writes raw bits to the field"]
352    #[inline]
353    pub fn bit(self, value: bool) -> &'a mut W {
354        const MASK: bool = true;
355        const OFFSET: u8 = 9;
356        self.w.bits &= !((MASK as u32) << OFFSET);
357        self.w.bits |= ((value & MASK) as u32) << OFFSET;
358        self.w
359    }
360}
361#[doc = r" Proxy"]
362pub struct _PEMISW<'a> {
363    w: &'a mut W,
364}
365impl<'a> _PEMISW<'a> {
366    #[doc = r" Sets the field bit"]
367    pub fn set_bit(self) -> &'a mut W {
368        self.bit(true)
369    }
370    #[doc = r" Clears the field bit"]
371    pub fn clear_bit(self) -> &'a mut W {
372        self.bit(false)
373    }
374    #[doc = r" Writes raw bits to the field"]
375    #[inline]
376    pub fn bit(self, value: bool) -> &'a mut W {
377        const MASK: bool = true;
378        const OFFSET: u8 = 8;
379        self.w.bits &= !((MASK as u32) << OFFSET);
380        self.w.bits |= ((value & MASK) as u32) << OFFSET;
381        self.w
382    }
383}
384#[doc = r" Proxy"]
385pub struct _FEMISW<'a> {
386    w: &'a mut W,
387}
388impl<'a> _FEMISW<'a> {
389    #[doc = r" Sets the field bit"]
390    pub fn set_bit(self) -> &'a mut W {
391        self.bit(true)
392    }
393    #[doc = r" Clears the field bit"]
394    pub fn clear_bit(self) -> &'a mut W {
395        self.bit(false)
396    }
397    #[doc = r" Writes raw bits to the field"]
398    #[inline]
399    pub fn bit(self, value: bool) -> &'a mut W {
400        const MASK: bool = true;
401        const OFFSET: u8 = 7;
402        self.w.bits &= !((MASK as u32) << OFFSET);
403        self.w.bits |= ((value & MASK) as u32) << OFFSET;
404        self.w
405    }
406}
407#[doc = r" Proxy"]
408pub struct _RTMISW<'a> {
409    w: &'a mut W,
410}
411impl<'a> _RTMISW<'a> {
412    #[doc = r" Sets the field bit"]
413    pub fn set_bit(self) -> &'a mut W {
414        self.bit(true)
415    }
416    #[doc = r" Clears the field bit"]
417    pub fn clear_bit(self) -> &'a mut W {
418        self.bit(false)
419    }
420    #[doc = r" Writes raw bits to the field"]
421    #[inline]
422    pub fn bit(self, value: bool) -> &'a mut W {
423        const MASK: bool = true;
424        const OFFSET: u8 = 6;
425        self.w.bits &= !((MASK as u32) << OFFSET);
426        self.w.bits |= ((value & MASK) as u32) << OFFSET;
427        self.w
428    }
429}
430#[doc = r" Proxy"]
431pub struct _TXMISW<'a> {
432    w: &'a mut W,
433}
434impl<'a> _TXMISW<'a> {
435    #[doc = r" Sets the field bit"]
436    pub fn set_bit(self) -> &'a mut W {
437        self.bit(true)
438    }
439    #[doc = r" Clears the field bit"]
440    pub fn clear_bit(self) -> &'a mut W {
441        self.bit(false)
442    }
443    #[doc = r" Writes raw bits to the field"]
444    #[inline]
445    pub fn bit(self, value: bool) -> &'a mut W {
446        const MASK: bool = true;
447        const OFFSET: u8 = 5;
448        self.w.bits &= !((MASK as u32) << OFFSET);
449        self.w.bits |= ((value & MASK) as u32) << OFFSET;
450        self.w
451    }
452}
453#[doc = r" Proxy"]
454pub struct _RXMISW<'a> {
455    w: &'a mut W,
456}
457impl<'a> _RXMISW<'a> {
458    #[doc = r" Sets the field bit"]
459    pub fn set_bit(self) -> &'a mut W {
460        self.bit(true)
461    }
462    #[doc = r" Clears the field bit"]
463    pub fn clear_bit(self) -> &'a mut W {
464        self.bit(false)
465    }
466    #[doc = r" Writes raw bits to the field"]
467    #[inline]
468    pub fn bit(self, value: bool) -> &'a mut W {
469        const MASK: bool = true;
470        const OFFSET: u8 = 4;
471        self.w.bits &= !((MASK as u32) << OFFSET);
472        self.w.bits |= ((value & MASK) as u32) << OFFSET;
473        self.w
474    }
475}
476#[doc = r" Proxy"]
477pub struct _RESERVED2W<'a> {
478    w: &'a mut W,
479}
480impl<'a> _RESERVED2W<'a> {
481    #[doc = r" Writes raw bits to the field"]
482    #[inline]
483    pub unsafe fn bits(self, value: u8) -> &'a mut W {
484        const MASK: u8 = 3;
485        const OFFSET: u8 = 2;
486        self.w.bits &= !((MASK as u32) << OFFSET);
487        self.w.bits |= ((value & MASK) as u32) << OFFSET;
488        self.w
489    }
490}
491#[doc = r" Proxy"]
492pub struct _CTSMMISW<'a> {
493    w: &'a mut W,
494}
495impl<'a> _CTSMMISW<'a> {
496    #[doc = r" Sets the field bit"]
497    pub fn set_bit(self) -> &'a mut W {
498        self.bit(true)
499    }
500    #[doc = r" Clears the field bit"]
501    pub fn clear_bit(self) -> &'a mut W {
502        self.bit(false)
503    }
504    #[doc = r" Writes raw bits to the field"]
505    #[inline]
506    pub fn bit(self, value: bool) -> &'a mut W {
507        const MASK: bool = true;
508        const OFFSET: u8 = 1;
509        self.w.bits &= !((MASK as u32) << OFFSET);
510        self.w.bits |= ((value & MASK) as u32) << OFFSET;
511        self.w
512    }
513}
514#[doc = r" Proxy"]
515pub struct _RESERVED0W<'a> {
516    w: &'a mut W,
517}
518impl<'a> _RESERVED0W<'a> {
519    #[doc = r" Sets the field bit"]
520    pub fn set_bit(self) -> &'a mut W {
521        self.bit(true)
522    }
523    #[doc = r" Clears the field bit"]
524    pub fn clear_bit(self) -> &'a mut W {
525        self.bit(false)
526    }
527    #[doc = r" Writes raw bits to the field"]
528    #[inline]
529    pub fn bit(self, value: bool) -> &'a mut W {
530        const MASK: bool = true;
531        const OFFSET: u8 = 0;
532        self.w.bits &= !((MASK as u32) << OFFSET);
533        self.w.bits |= ((value & MASK) as u32) << OFFSET;
534        self.w
535    }
536}
537impl R {
538    #[doc = r" Value of the register as raw bits"]
539    #[inline]
540    pub fn bits(&self) -> u32 {
541        self.bits
542    }
543    #[doc = "Bits 12:31 - 31:12\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
544    #[inline]
545    pub fn reserved12(&self) -> RESERVED12R {
546        let bits = {
547            const MASK: u32 = 1048575;
548            const OFFSET: u8 = 12;
549            ((self.bits >> OFFSET) & MASK as u32) as u32
550        };
551        RESERVED12R { bits }
552    }
553    #[doc = "Bit 11 - 11:11\\] End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM."]
554    #[inline]
555    pub fn eotmis(&self) -> EOTMISR {
556        let bits = {
557            const MASK: bool = true;
558            const OFFSET: u8 = 11;
559            ((self.bits >> OFFSET) & MASK as u32) != 0
560        };
561        EOTMISR { bits }
562    }
563    #[doc = "Bit 10 - 10:10\\] Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM."]
564    #[inline]
565    pub fn oemis(&self) -> OEMISR {
566        let bits = {
567            const MASK: bool = true;
568            const OFFSET: u8 = 10;
569            ((self.bits >> OFFSET) & MASK as u32) != 0
570        };
571        OEMISR { bits }
572    }
573    #[doc = "Bit 9 - 9:9\\] Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM."]
574    #[inline]
575    pub fn bemis(&self) -> BEMISR {
576        let bits = {
577            const MASK: bool = true;
578            const OFFSET: u8 = 9;
579            ((self.bits >> OFFSET) & MASK as u32) != 0
580        };
581        BEMISR { bits }
582    }
583    #[doc = "Bit 8 - 8:8\\] Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM."]
584    #[inline]
585    pub fn pemis(&self) -> PEMISR {
586        let bits = {
587            const MASK: bool = true;
588            const OFFSET: u8 = 8;
589            ((self.bits >> OFFSET) & MASK as u32) != 0
590        };
591        PEMISR { bits }
592    }
593    #[doc = "Bit 7 - 7:7\\] Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM."]
594    #[inline]
595    pub fn femis(&self) -> FEMISR {
596        let bits = {
597            const MASK: bool = true;
598            const OFFSET: u8 = 7;
599            ((self.bits >> OFFSET) & MASK as u32) != 0
600        };
601        FEMISR { bits }
602    }
603    #[doc = "Bit 6 - 6:6\\] Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS."]
604    #[inline]
605    pub fn rtmis(&self) -> RTMISR {
606        let bits = {
607            const MASK: bool = true;
608            const OFFSET: u8 = 6;
609            ((self.bits >> OFFSET) & MASK as u32) != 0
610        };
611        RTMISR { bits }
612    }
613    #[doc = "Bit 5 - 5:5\\] Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM."]
614    #[inline]
615    pub fn txmis(&self) -> TXMISR {
616        let bits = {
617            const MASK: bool = true;
618            const OFFSET: u8 = 5;
619            ((self.bits >> OFFSET) & MASK as u32) != 0
620        };
621        TXMISR { bits }
622    }
623    #[doc = "Bit 4 - 4:4\\] Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM."]
624    #[inline]
625    pub fn rxmis(&self) -> RXMISR {
626        let bits = {
627            const MASK: bool = true;
628            const OFFSET: u8 = 4;
629            ((self.bits >> OFFSET) & MASK as u32) != 0
630        };
631        RXMISR { bits }
632    }
633    #[doc = "Bits 2:3 - 3:2\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
634    #[inline]
635    pub fn reserved2(&self) -> RESERVED2R {
636        let bits = {
637            const MASK: u8 = 3;
638            const OFFSET: u8 = 2;
639            ((self.bits >> OFFSET) & MASK as u32) as u8
640        };
641        RESERVED2R { bits }
642    }
643    #[doc = "Bit 1 - 1:1\\] Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM."]
644    #[inline]
645    pub fn ctsmmis(&self) -> CTSMMISR {
646        let bits = {
647            const MASK: bool = true;
648            const OFFSET: u8 = 1;
649            ((self.bits >> OFFSET) & MASK as u32) != 0
650        };
651        CTSMMISR { bits }
652    }
653    #[doc = "Bit 0 - 0:0\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
654    #[inline]
655    pub fn reserved0(&self) -> RESERVED0R {
656        let bits = {
657            const MASK: bool = true;
658            const OFFSET: u8 = 0;
659            ((self.bits >> OFFSET) & MASK as u32) != 0
660        };
661        RESERVED0R { bits }
662    }
663}
664impl W {
665    #[doc = r" Reset value of the register"]
666    #[inline]
667    pub fn reset_value() -> W {
668        W { bits: 0 }
669    }
670    #[doc = r" Writes raw bits to the register"]
671    #[inline]
672    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
673        self.bits = bits;
674        self
675    }
676    #[doc = "Bits 12:31 - 31:12\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
677    #[inline]
678    pub fn reserved12(&mut self) -> _RESERVED12W {
679        _RESERVED12W { w: self }
680    }
681    #[doc = "Bit 11 - 11:11\\] End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM."]
682    #[inline]
683    pub fn eotmis(&mut self) -> _EOTMISW {
684        _EOTMISW { w: self }
685    }
686    #[doc = "Bit 10 - 10:10\\] Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM."]
687    #[inline]
688    pub fn oemis(&mut self) -> _OEMISW {
689        _OEMISW { w: self }
690    }
691    #[doc = "Bit 9 - 9:9\\] Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM."]
692    #[inline]
693    pub fn bemis(&mut self) -> _BEMISW {
694        _BEMISW { w: self }
695    }
696    #[doc = "Bit 8 - 8:8\\] Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM."]
697    #[inline]
698    pub fn pemis(&mut self) -> _PEMISW {
699        _PEMISW { w: self }
700    }
701    #[doc = "Bit 7 - 7:7\\] Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM."]
702    #[inline]
703    pub fn femis(&mut self) -> _FEMISW {
704        _FEMISW { w: self }
705    }
706    #[doc = "Bit 6 - 6:6\\] Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS."]
707    #[inline]
708    pub fn rtmis(&mut self) -> _RTMISW {
709        _RTMISW { w: self }
710    }
711    #[doc = "Bit 5 - 5:5\\] Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM."]
712    #[inline]
713    pub fn txmis(&mut self) -> _TXMISW {
714        _TXMISW { w: self }
715    }
716    #[doc = "Bit 4 - 4:4\\] Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM."]
717    #[inline]
718    pub fn rxmis(&mut self) -> _RXMISW {
719        _RXMISW { w: self }
720    }
721    #[doc = "Bits 2:3 - 3:2\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
722    #[inline]
723    pub fn reserved2(&mut self) -> _RESERVED2W {
724        _RESERVED2W { w: self }
725    }
726    #[doc = "Bit 1 - 1:1\\] Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM."]
727    #[inline]
728    pub fn ctsmmis(&mut self) -> _CTSMMISW {
729        _CTSMMISW { w: self }
730    }
731    #[doc = "Bit 0 - 0:0\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
732    #[inline]
733    pub fn reserved0(&mut self) -> _RESERVED0W {
734        _RESERVED0W { w: self }
735    }
736}
cc13x2_cc26x2_pac/uart0/mis.rs

cc13x2_cc26x2_pac/uart0/
mis.rs
