cc13x2_cc26x2_pac/ccfg/
size_and_dis_flags.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SIZE_AND_DIS_FLAGS {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct SIZE_OF_CCFGR {
47    bits: u16,
48}
49impl SIZE_OF_CCFGR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u16 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct DISABLE_FLAGSR {
58    bits: u16,
59}
60impl DISABLE_FLAGSR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bits(&self) -> u16 {
64        self.bits
65    }
66}
67#[doc = r" Value of the field"]
68pub struct DIS_TCXOR {
69    bits: bool,
70}
71impl DIS_TCXOR {
72    #[doc = r" Value of the field as raw bits"]
73    #[inline]
74    pub fn bit(&self) -> bool {
75        self.bits
76    }
77    #[doc = r" Returns `true` if the bit is clear (0)"]
78    #[inline]
79    pub fn bit_is_clear(&self) -> bool {
80        !self.bit()
81    }
82    #[doc = r" Returns `true` if the bit is set (1)"]
83    #[inline]
84    pub fn bit_is_set(&self) -> bool {
85        self.bit()
86    }
87}
88#[doc = r" Value of the field"]
89pub struct DIS_GPRAMR {
90    bits: bool,
91}
92impl DIS_GPRAMR {
93    #[doc = r" Value of the field as raw bits"]
94    #[inline]
95    pub fn bit(&self) -> bool {
96        self.bits
97    }
98    #[doc = r" Returns `true` if the bit is clear (0)"]
99    #[inline]
100    pub fn bit_is_clear(&self) -> bool {
101        !self.bit()
102    }
103    #[doc = r" Returns `true` if the bit is set (1)"]
104    #[inline]
105    pub fn bit_is_set(&self) -> bool {
106        self.bit()
107    }
108}
109#[doc = r" Value of the field"]
110pub struct DIS_ALT_DCDC_SETTINGR {
111    bits: bool,
112}
113impl DIS_ALT_DCDC_SETTINGR {
114    #[doc = r" Value of the field as raw bits"]
115    #[inline]
116    pub fn bit(&self) -> bool {
117        self.bits
118    }
119    #[doc = r" Returns `true` if the bit is clear (0)"]
120    #[inline]
121    pub fn bit_is_clear(&self) -> bool {
122        !self.bit()
123    }
124    #[doc = r" Returns `true` if the bit is set (1)"]
125    #[inline]
126    pub fn bit_is_set(&self) -> bool {
127        self.bit()
128    }
129}
130#[doc = r" Value of the field"]
131pub struct DIS_XOSC_OVRR {
132    bits: bool,
133}
134impl DIS_XOSC_OVRR {
135    #[doc = r" Value of the field as raw bits"]
136    #[inline]
137    pub fn bit(&self) -> bool {
138        self.bits
139    }
140    #[doc = r" Returns `true` if the bit is clear (0)"]
141    #[inline]
142    pub fn bit_is_clear(&self) -> bool {
143        !self.bit()
144    }
145    #[doc = r" Returns `true` if the bit is set (1)"]
146    #[inline]
147    pub fn bit_is_set(&self) -> bool {
148        self.bit()
149    }
150}
151#[doc = r" Proxy"]
152pub struct _SIZE_OF_CCFGW<'a> {
153    w: &'a mut W,
154}
155impl<'a> _SIZE_OF_CCFGW<'a> {
156    #[doc = r" Writes raw bits to the field"]
157    #[inline]
158    pub unsafe fn bits(self, value: u16) -> &'a mut W {
159        const MASK: u16 = 65535;
160        const OFFSET: u8 = 16;
161        self.w.bits &= !((MASK as u32) << OFFSET);
162        self.w.bits |= ((value & MASK) as u32) << OFFSET;
163        self.w
164    }
165}
166#[doc = r" Proxy"]
167pub struct _DISABLE_FLAGSW<'a> {
168    w: &'a mut W,
169}
170impl<'a> _DISABLE_FLAGSW<'a> {
171    #[doc = r" Writes raw bits to the field"]
172    #[inline]
173    pub unsafe fn bits(self, value: u16) -> &'a mut W {
174        const MASK: u16 = 4095;
175        const OFFSET: u8 = 4;
176        self.w.bits &= !((MASK as u32) << OFFSET);
177        self.w.bits |= ((value & MASK) as u32) << OFFSET;
178        self.w
179    }
180}
181#[doc = r" Proxy"]
182pub struct _DIS_TCXOW<'a> {
183    w: &'a mut W,
184}
185impl<'a> _DIS_TCXOW<'a> {
186    #[doc = r" Sets the field bit"]
187    pub fn set_bit(self) -> &'a mut W {
188        self.bit(true)
189    }
190    #[doc = r" Clears the field bit"]
191    pub fn clear_bit(self) -> &'a mut W {
192        self.bit(false)
193    }
194    #[doc = r" Writes raw bits to the field"]
195    #[inline]
196    pub fn bit(self, value: bool) -> &'a mut W {
197        const MASK: bool = true;
198        const OFFSET: u8 = 3;
199        self.w.bits &= !((MASK as u32) << OFFSET);
200        self.w.bits |= ((value & MASK) as u32) << OFFSET;
201        self.w
202    }
203}
204#[doc = r" Proxy"]
205pub struct _DIS_GPRAMW<'a> {
206    w: &'a mut W,
207}
208impl<'a> _DIS_GPRAMW<'a> {
209    #[doc = r" Sets the field bit"]
210    pub fn set_bit(self) -> &'a mut W {
211        self.bit(true)
212    }
213    #[doc = r" Clears the field bit"]
214    pub fn clear_bit(self) -> &'a mut W {
215        self.bit(false)
216    }
217    #[doc = r" Writes raw bits to the field"]
218    #[inline]
219    pub fn bit(self, value: bool) -> &'a mut W {
220        const MASK: bool = true;
221        const OFFSET: u8 = 2;
222        self.w.bits &= !((MASK as u32) << OFFSET);
223        self.w.bits |= ((value & MASK) as u32) << OFFSET;
224        self.w
225    }
226}
227#[doc = r" Proxy"]
228pub struct _DIS_ALT_DCDC_SETTINGW<'a> {
229    w: &'a mut W,
230}
231impl<'a> _DIS_ALT_DCDC_SETTINGW<'a> {
232    #[doc = r" Sets the field bit"]
233    pub fn set_bit(self) -> &'a mut W {
234        self.bit(true)
235    }
236    #[doc = r" Clears the field bit"]
237    pub fn clear_bit(self) -> &'a mut W {
238        self.bit(false)
239    }
240    #[doc = r" Writes raw bits to the field"]
241    #[inline]
242    pub fn bit(self, value: bool) -> &'a mut W {
243        const MASK: bool = true;
244        const OFFSET: u8 = 1;
245        self.w.bits &= !((MASK as u32) << OFFSET);
246        self.w.bits |= ((value & MASK) as u32) << OFFSET;
247        self.w
248    }
249}
250#[doc = r" Proxy"]
251pub struct _DIS_XOSC_OVRW<'a> {
252    w: &'a mut W,
253}
254impl<'a> _DIS_XOSC_OVRW<'a> {
255    #[doc = r" Sets the field bit"]
256    pub fn set_bit(self) -> &'a mut W {
257        self.bit(true)
258    }
259    #[doc = r" Clears the field bit"]
260    pub fn clear_bit(self) -> &'a mut W {
261        self.bit(false)
262    }
263    #[doc = r" Writes raw bits to the field"]
264    #[inline]
265    pub fn bit(self, value: bool) -> &'a mut W {
266        const MASK: bool = true;
267        const OFFSET: u8 = 0;
268        self.w.bits &= !((MASK as u32) << OFFSET);
269        self.w.bits |= ((value & MASK) as u32) << OFFSET;
270        self.w
271    }
272}
273impl R {
274    #[doc = r" Value of the register as raw bits"]
275    #[inline]
276    pub fn bits(&self) -> u32 {
277        self.bits
278    }
279    #[doc = "Bits 16:31 - 31:16\\] Total size of CCFG in bytes."]
280    #[inline]
281    pub fn size_of_ccfg(&self) -> SIZE_OF_CCFGR {
282        let bits = {
283            const MASK: u16 = 65535;
284            const OFFSET: u8 = 16;
285            ((self.bits >> OFFSET) & MASK as u32) as u16
286        };
287        SIZE_OF_CCFGR { bits }
288    }
289    #[doc = "Bits 4:15 - 15:4\\] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior."]
290    #[inline]
291    pub fn disable_flags(&self) -> DISABLE_FLAGSR {
292        let bits = {
293            const MASK: u16 = 4095;
294            const OFFSET: u8 = 4;
295            ((self.bits >> OFFSET) & MASK as u32) as u16
296        };
297        DISABLE_FLAGSR { bits }
298    }
299    #[doc = "Bit 3 - 3:3\\] Disable TCXO. 0: TCXO functionality enabled. 1: TCXO functionality disabled. Note: An external TCXO is required if DIS_TCXO = 0."]
300    #[inline]
301    pub fn dis_tcxo(&self) -> DIS_TCXOR {
302        let bits = {
303            const MASK: bool = true;
304            const OFFSET: u8 = 3;
305            ((self.bits >> OFFSET) & MASK as u32) != 0
306        };
307        DIS_TCXOR { bits }
308    }
309    #[doc = "Bit 2 - 2:2\\] Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 0: GPRAM is enabled and hence CACHE disabled. 1: GPRAM is disabled and instead CACHE is enabled (default). Notes: - Disabling CACHE will reduce CPU execution speed (up to 60%). - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled. See: VIMS:CTL.MODE"]
310    #[inline]
311    pub fn dis_gpram(&self) -> DIS_GPRAMR {
312        let bits = {
313            const MASK: bool = true;
314            const OFFSET: u8 = 2;
315            ((self.bits >> OFFSET) & MASK as u32) != 0
316        };
317        DIS_GPRAMR { bits }
318    }
319    #[doc = "Bit 1 - 1:1\\] Disable alternate DC/DC settings. 0: Enable alternate DC/DC settings. 1: Disable alternate DC/DC settings. See: MODE_CONF_1.ALT_DCDC_VMIN MODE_CONF_1.ALT_DCDC_DITHER_EN MODE_CONF_1.ALT_DCDC_IPEAK NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!)."]
320    #[inline]
321    pub fn dis_alt_dcdc_setting(&self) -> DIS_ALT_DCDC_SETTINGR {
322        let bits = {
323            const MASK: bool = true;
324            const OFFSET: u8 = 1;
325            ((self.bits >> OFFSET) & MASK as u32) != 0
326        };
327        DIS_ALT_DCDC_SETTINGR { bits }
328    }
329    #[doc = "Bit 0 - 0:0\\] Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START"]
330    #[inline]
331    pub fn dis_xosc_ovr(&self) -> DIS_XOSC_OVRR {
332        let bits = {
333            const MASK: bool = true;
334            const OFFSET: u8 = 0;
335            ((self.bits >> OFFSET) & MASK as u32) != 0
336        };
337        DIS_XOSC_OVRR { bits }
338    }
339}
340impl W {
341    #[doc = r" Reset value of the register"]
342    #[inline]
343    pub fn reset_value() -> W {
344        W { bits: 4294967295 }
345    }
346    #[doc = r" Writes raw bits to the register"]
347    #[inline]
348    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
349        self.bits = bits;
350        self
351    }
352    #[doc = "Bits 16:31 - 31:16\\] Total size of CCFG in bytes."]
353    #[inline]
354    pub fn size_of_ccfg(&mut self) -> _SIZE_OF_CCFGW {
355        _SIZE_OF_CCFGW { w: self }
356    }
357    #[doc = "Bits 4:15 - 15:4\\] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior."]
358    #[inline]
359    pub fn disable_flags(&mut self) -> _DISABLE_FLAGSW {
360        _DISABLE_FLAGSW { w: self }
361    }
362    #[doc = "Bit 3 - 3:3\\] Disable TCXO. 0: TCXO functionality enabled. 1: TCXO functionality disabled. Note: An external TCXO is required if DIS_TCXO = 0."]
363    #[inline]
364    pub fn dis_tcxo(&mut self) -> _DIS_TCXOW {
365        _DIS_TCXOW { w: self }
366    }
367    #[doc = "Bit 2 - 2:2\\] Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 0: GPRAM is enabled and hence CACHE disabled. 1: GPRAM is disabled and instead CACHE is enabled (default). Notes: - Disabling CACHE will reduce CPU execution speed (up to 60%). - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled. See: VIMS:CTL.MODE"]
368    #[inline]
369    pub fn dis_gpram(&mut self) -> _DIS_GPRAMW {
370        _DIS_GPRAMW { w: self }
371    }
372    #[doc = "Bit 1 - 1:1\\] Disable alternate DC/DC settings. 0: Enable alternate DC/DC settings. 1: Disable alternate DC/DC settings. See: MODE_CONF_1.ALT_DCDC_VMIN MODE_CONF_1.ALT_DCDC_DITHER_EN MODE_CONF_1.ALT_DCDC_IPEAK NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!)."]
373    #[inline]
374    pub fn dis_alt_dcdc_setting(&mut self) -> _DIS_ALT_DCDC_SETTINGW {
375        _DIS_ALT_DCDC_SETTINGW { w: self }
376    }
377    #[doc = "Bit 0 - 0:0\\] Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START"]
378    #[inline]
379    pub fn dis_xosc_ovr(&mut self) -> _DIS_XOSC_OVRW {
380        _DIS_XOSC_OVRW { w: self }
381    }
382}
cc13x2_cc26x2_pac/ccfg/size_and_dis_flags.rs

cc13x2_cc26x2_pac/ccfg/
size_and_dis_flags.rs
