Module cc13x2_cc26x2_pac::crypto::dmastat

DMAC Status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer.

Structs

CH0_ACTR	Value of the field
CH1_ACTR	Value of the field
PORT_ERRR	Value of the field
R	Value read from the register
RESERVED2R	Value of the field
RESERVED18R	Value of the field
W	Value to write to the register
_CH0_ACTW	Proxy
_CH1_ACTW	Proxy
_PORT_ERRW	Proxy
_RESERVED2W	Proxy
_RESERVED18W	Proxy