cc13x2_cc26x2_pac/prcm/
uartclkgr.rs1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::UARTCLKGR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct RESERVED10R {
47 bits: u32,
48}
49impl RESERVED10R {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u32 {
53 self.bits
54 }
55}
56#[doc = "Possible values of the field `AM_CLK_EN`"]
57#[derive(Clone, Copy, Debug, PartialEq)]
58pub enum AM_CLK_ENR {
59 #[doc = "Enable clock for UART1"]
60 AM_UART1,
61 #[doc = "Enable clock for UART0"]
62 AM_UART0,
63 #[doc = r" Reserved"]
64 _Reserved(u8),
65}
66impl AM_CLK_ENR {
67 #[doc = r" Value of the field as raw bits"]
68 #[inline]
69 pub fn bits(&self) -> u8 {
70 match *self {
71 AM_CLK_ENR::AM_UART1 => 2,
72 AM_CLK_ENR::AM_UART0 => 1,
73 AM_CLK_ENR::_Reserved(bits) => bits,
74 }
75 }
76 #[allow(missing_docs)]
77 #[doc(hidden)]
78 #[inline]
79 pub fn _from(value: u8) -> AM_CLK_ENR {
80 match value {
81 2 => AM_CLK_ENR::AM_UART1,
82 1 => AM_CLK_ENR::AM_UART0,
83 i => AM_CLK_ENR::_Reserved(i),
84 }
85 }
86 #[doc = "Checks if the value of the field is `AM_UART1`"]
87 #[inline]
88 pub fn is_am_uart1(&self) -> bool {
89 *self == AM_CLK_ENR::AM_UART1
90 }
91 #[doc = "Checks if the value of the field is `AM_UART0`"]
92 #[inline]
93 pub fn is_am_uart0(&self) -> bool {
94 *self == AM_CLK_ENR::AM_UART0
95 }
96}
97#[doc = r" Value of the field"]
98pub struct RESERVED2R {
99 bits: u8,
100}
101impl RESERVED2R {
102 #[doc = r" Value of the field as raw bits"]
103 #[inline]
104 pub fn bits(&self) -> u8 {
105 self.bits
106 }
107}
108#[doc = "Possible values of the field `CLK_EN`"]
109#[derive(Clone, Copy, Debug, PartialEq)]
110pub enum CLK_ENR {
111 #[doc = "Enable clock for UART1"]
112 UART1,
113 #[doc = "Enable clock for UART0"]
114 UART0,
115 #[doc = r" Reserved"]
116 _Reserved(u8),
117}
118impl CLK_ENR {
119 #[doc = r" Value of the field as raw bits"]
120 #[inline]
121 pub fn bits(&self) -> u8 {
122 match *self {
123 CLK_ENR::UART1 => 2,
124 CLK_ENR::UART0 => 1,
125 CLK_ENR::_Reserved(bits) => bits,
126 }
127 }
128 #[allow(missing_docs)]
129 #[doc(hidden)]
130 #[inline]
131 pub fn _from(value: u8) -> CLK_ENR {
132 match value {
133 2 => CLK_ENR::UART1,
134 1 => CLK_ENR::UART0,
135 i => CLK_ENR::_Reserved(i),
136 }
137 }
138 #[doc = "Checks if the value of the field is `UART1`"]
139 #[inline]
140 pub fn is_uart1(&self) -> bool {
141 *self == CLK_ENR::UART1
142 }
143 #[doc = "Checks if the value of the field is `UART0`"]
144 #[inline]
145 pub fn is_uart0(&self) -> bool {
146 *self == CLK_ENR::UART0
147 }
148}
149#[doc = r" Proxy"]
150pub struct _RESERVED10W<'a> {
151 w: &'a mut W,
152}
153impl<'a> _RESERVED10W<'a> {
154 #[doc = r" Writes raw bits to the field"]
155 #[inline]
156 pub unsafe fn bits(self, value: u32) -> &'a mut W {
157 const MASK: u32 = 4194303;
158 const OFFSET: u8 = 10;
159 self.w.bits &= !((MASK as u32) << OFFSET);
160 self.w.bits |= ((value & MASK) as u32) << OFFSET;
161 self.w
162 }
163}
164#[doc = "Values that can be written to the field `AM_CLK_EN`"]
165pub enum AM_CLK_ENW {
166 #[doc = "Enable clock for UART1"]
167 AM_UART1,
168 #[doc = "Enable clock for UART0"]
169 AM_UART0,
170}
171impl AM_CLK_ENW {
172 #[allow(missing_docs)]
173 #[doc(hidden)]
174 #[inline]
175 pub fn _bits(&self) -> u8 {
176 match *self {
177 AM_CLK_ENW::AM_UART1 => 2,
178 AM_CLK_ENW::AM_UART0 => 1,
179 }
180 }
181}
182#[doc = r" Proxy"]
183pub struct _AM_CLK_ENW<'a> {
184 w: &'a mut W,
185}
186impl<'a> _AM_CLK_ENW<'a> {
187 #[doc = r" Writes `variant` to the field"]
188 #[inline]
189 pub fn variant(self, variant: AM_CLK_ENW) -> &'a mut W {
190 unsafe { self.bits(variant._bits()) }
191 }
192 #[doc = "Enable clock for UART1"]
193 #[inline]
194 pub fn am_uart1(self) -> &'a mut W {
195 self.variant(AM_CLK_ENW::AM_UART1)
196 }
197 #[doc = "Enable clock for UART0"]
198 #[inline]
199 pub fn am_uart0(self) -> &'a mut W {
200 self.variant(AM_CLK_ENW::AM_UART0)
201 }
202 #[doc = r" Writes raw bits to the field"]
203 #[inline]
204 pub unsafe fn bits(self, value: u8) -> &'a mut W {
205 const MASK: u8 = 3;
206 const OFFSET: u8 = 8;
207 self.w.bits &= !((MASK as u32) << OFFSET);
208 self.w.bits |= ((value & MASK) as u32) << OFFSET;
209 self.w
210 }
211}
212#[doc = r" Proxy"]
213pub struct _RESERVED2W<'a> {
214 w: &'a mut W,
215}
216impl<'a> _RESERVED2W<'a> {
217 #[doc = r" Writes raw bits to the field"]
218 #[inline]
219 pub unsafe fn bits(self, value: u8) -> &'a mut W {
220 const MASK: u8 = 63;
221 const OFFSET: u8 = 2;
222 self.w.bits &= !((MASK as u32) << OFFSET);
223 self.w.bits |= ((value & MASK) as u32) << OFFSET;
224 self.w
225 }
226}
227#[doc = "Values that can be written to the field `CLK_EN`"]
228pub enum CLK_ENW {
229 #[doc = "Enable clock for UART1"]
230 UART1,
231 #[doc = "Enable clock for UART0"]
232 UART0,
233}
234impl CLK_ENW {
235 #[allow(missing_docs)]
236 #[doc(hidden)]
237 #[inline]
238 pub fn _bits(&self) -> u8 {
239 match *self {
240 CLK_ENW::UART1 => 2,
241 CLK_ENW::UART0 => 1,
242 }
243 }
244}
245#[doc = r" Proxy"]
246pub struct _CLK_ENW<'a> {
247 w: &'a mut W,
248}
249impl<'a> _CLK_ENW<'a> {
250 #[doc = r" Writes `variant` to the field"]
251 #[inline]
252 pub fn variant(self, variant: CLK_ENW) -> &'a mut W {
253 unsafe { self.bits(variant._bits()) }
254 }
255 #[doc = "Enable clock for UART1"]
256 #[inline]
257 pub fn uart1(self) -> &'a mut W {
258 self.variant(CLK_ENW::UART1)
259 }
260 #[doc = "Enable clock for UART0"]
261 #[inline]
262 pub fn uart0(self) -> &'a mut W {
263 self.variant(CLK_ENW::UART0)
264 }
265 #[doc = r" Writes raw bits to the field"]
266 #[inline]
267 pub unsafe fn bits(self, value: u8) -> &'a mut W {
268 const MASK: u8 = 3;
269 const OFFSET: u8 = 0;
270 self.w.bits &= !((MASK as u32) << OFFSET);
271 self.w.bits |= ((value & MASK) as u32) << OFFSET;
272 self.w
273 }
274}
275impl R {
276 #[doc = r" Value of the register as raw bits"]
277 #[inline]
278 pub fn bits(&self) -> u32 {
279 self.bits
280 }
281 #[doc = "Bits 10:31 - 31:10\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
282 #[inline]
283 pub fn reserved10(&self) -> RESERVED10R {
284 let bits = {
285 const MASK: u32 = 4194303;
286 const OFFSET: u8 = 10;
287 ((self.bits >> OFFSET) & MASK as u32) as u32
288 };
289 RESERVED10R { bits }
290 }
291 #[doc = "Bits 8:9 - 9:8\\] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
292 #[inline]
293 pub fn am_clk_en(&self) -> AM_CLK_ENR {
294 AM_CLK_ENR::_from({
295 const MASK: u8 = 3;
296 const OFFSET: u8 = 8;
297 ((self.bits >> OFFSET) & MASK as u32) as u8
298 })
299 }
300 #[doc = "Bits 2:7 - 7:2\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
301 #[inline]
302 pub fn reserved2(&self) -> RESERVED2R {
303 let bits = {
304 const MASK: u8 = 63;
305 const OFFSET: u8 = 2;
306 ((self.bits >> OFFSET) & MASK as u32) as u8
307 };
308 RESERVED2R { bits }
309 }
310 #[doc = "Bits 0:1 - 1:0\\] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
311 #[inline]
312 pub fn clk_en(&self) -> CLK_ENR {
313 CLK_ENR::_from({
314 const MASK: u8 = 3;
315 const OFFSET: u8 = 0;
316 ((self.bits >> OFFSET) & MASK as u32) as u8
317 })
318 }
319}
320impl W {
321 #[doc = r" Reset value of the register"]
322 #[inline]
323 pub fn reset_value() -> W {
324 W { bits: 0 }
325 }
326 #[doc = r" Writes raw bits to the register"]
327 #[inline]
328 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
329 self.bits = bits;
330 self
331 }
332 #[doc = "Bits 10:31 - 31:10\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
333 #[inline]
334 pub fn reserved10(&mut self) -> _RESERVED10W {
335 _RESERVED10W { w: self }
336 }
337 #[doc = "Bits 8:9 - 9:8\\] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
338 #[inline]
339 pub fn am_clk_en(&mut self) -> _AM_CLK_ENW {
340 _AM_CLK_ENW { w: self }
341 }
342 #[doc = "Bits 2:7 - 7:2\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
343 #[inline]
344 pub fn reserved2(&mut self) -> _RESERVED2W {
345 _RESERVED2W { w: self }
346 }
347 #[doc = "Bits 0:1 - 1:0\\] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written"]
348 #[inline]
349 pub fn clk_en(&mut self) -> _CLK_ENW {
350 _CLK_ENW { w: self }
351 }
352}