1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::IOCFG5 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct RESERVED31R {
47 bits: bool,
48}
49impl RESERVED31R {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bit(&self) -> bool {
53 self.bits
54 }
55 #[doc = r" Returns `true` if the bit is clear (0)"]
56 #[inline]
57 pub fn bit_is_clear(&self) -> bool {
58 !self.bit()
59 }
60 #[doc = r" Returns `true` if the bit is set (1)"]
61 #[inline]
62 pub fn bit_is_set(&self) -> bool {
63 self.bit()
64 }
65}
66#[doc = r" Value of the field"]
67pub struct HYST_ENR {
68 bits: bool,
69}
70impl HYST_ENR {
71 #[doc = r" Value of the field as raw bits"]
72 #[inline]
73 pub fn bit(&self) -> bool {
74 self.bits
75 }
76 #[doc = r" Returns `true` if the bit is clear (0)"]
77 #[inline]
78 pub fn bit_is_clear(&self) -> bool {
79 !self.bit()
80 }
81 #[doc = r" Returns `true` if the bit is set (1)"]
82 #[inline]
83 pub fn bit_is_set(&self) -> bool {
84 self.bit()
85 }
86}
87#[doc = r" Value of the field"]
88pub struct IER {
89 bits: bool,
90}
91impl IER {
92 #[doc = r" Value of the field as raw bits"]
93 #[inline]
94 pub fn bit(&self) -> bool {
95 self.bits
96 }
97 #[doc = r" Returns `true` if the bit is clear (0)"]
98 #[inline]
99 pub fn bit_is_clear(&self) -> bool {
100 !self.bit()
101 }
102 #[doc = r" Returns `true` if the bit is set (1)"]
103 #[inline]
104 pub fn bit_is_set(&self) -> bool {
105 self.bit()
106 }
107}
108#[doc = r" Value of the field"]
109pub struct WU_CFGR {
110 bits: u8,
111}
112impl WU_CFGR {
113 #[doc = r" Value of the field as raw bits"]
114 #[inline]
115 pub fn bits(&self) -> u8 {
116 self.bits
117 }
118}
119#[doc = "Possible values of the field `IOMODE`"]
120#[derive(Clone, Copy, Debug, PartialEq)]
121pub enum IOMODER {
122 #[doc = "Open Source\nInverted input / output"]
123 OPENSRC_INV,
124 #[doc = "Open Source\nNormal input / output"]
125 OPENSRC,
126 #[doc = "Open Drain\nInverted input / output"]
127 OPENDR_INV,
128 #[doc = "Open Drain, \nNormal input / output"]
129 OPENDR,
130 #[doc = "Inverted input / ouput"]
131 INV,
132 #[doc = "Normal input / output"]
133 NORMAL,
134 #[doc = r" Reserved"]
135 _Reserved(u8),
136}
137impl IOMODER {
138 #[doc = r" Value of the field as raw bits"]
139 #[inline]
140 pub fn bits(&self) -> u8 {
141 match *self {
142 IOMODER::OPENSRC_INV => 7,
143 IOMODER::OPENSRC => 6,
144 IOMODER::OPENDR_INV => 5,
145 IOMODER::OPENDR => 4,
146 IOMODER::INV => 1,
147 IOMODER::NORMAL => 0,
148 IOMODER::_Reserved(bits) => bits,
149 }
150 }
151 #[allow(missing_docs)]
152 #[doc(hidden)]
153 #[inline]
154 pub fn _from(value: u8) -> IOMODER {
155 match value {
156 7 => IOMODER::OPENSRC_INV,
157 6 => IOMODER::OPENSRC,
158 5 => IOMODER::OPENDR_INV,
159 4 => IOMODER::OPENDR,
160 1 => IOMODER::INV,
161 0 => IOMODER::NORMAL,
162 i => IOMODER::_Reserved(i),
163 }
164 }
165 #[doc = "Checks if the value of the field is `OPENSRC_INV`"]
166 #[inline]
167 pub fn is_opensrc_inv(&self) -> bool {
168 *self == IOMODER::OPENSRC_INV
169 }
170 #[doc = "Checks if the value of the field is `OPENSRC`"]
171 #[inline]
172 pub fn is_opensrc(&self) -> bool {
173 *self == IOMODER::OPENSRC
174 }
175 #[doc = "Checks if the value of the field is `OPENDR_INV`"]
176 #[inline]
177 pub fn is_opendr_inv(&self) -> bool {
178 *self == IOMODER::OPENDR_INV
179 }
180 #[doc = "Checks if the value of the field is `OPENDR`"]
181 #[inline]
182 pub fn is_opendr(&self) -> bool {
183 *self == IOMODER::OPENDR
184 }
185 #[doc = "Checks if the value of the field is `INV`"]
186 #[inline]
187 pub fn is_inv(&self) -> bool {
188 *self == IOMODER::INV
189 }
190 #[doc = "Checks if the value of the field is `NORMAL`"]
191 #[inline]
192 pub fn is_normal(&self) -> bool {
193 *self == IOMODER::NORMAL
194 }
195}
196#[doc = r" Value of the field"]
197pub struct IOEV_AON_PROG2_ENR {
198 bits: bool,
199}
200impl IOEV_AON_PROG2_ENR {
201 #[doc = r" Value of the field as raw bits"]
202 #[inline]
203 pub fn bit(&self) -> bool {
204 self.bits
205 }
206 #[doc = r" Returns `true` if the bit is clear (0)"]
207 #[inline]
208 pub fn bit_is_clear(&self) -> bool {
209 !self.bit()
210 }
211 #[doc = r" Returns `true` if the bit is set (1)"]
212 #[inline]
213 pub fn bit_is_set(&self) -> bool {
214 self.bit()
215 }
216}
217#[doc = r" Value of the field"]
218pub struct IOEV_AON_PROG1_ENR {
219 bits: bool,
220}
221impl IOEV_AON_PROG1_ENR {
222 #[doc = r" Value of the field as raw bits"]
223 #[inline]
224 pub fn bit(&self) -> bool {
225 self.bits
226 }
227 #[doc = r" Returns `true` if the bit is clear (0)"]
228 #[inline]
229 pub fn bit_is_clear(&self) -> bool {
230 !self.bit()
231 }
232 #[doc = r" Returns `true` if the bit is set (1)"]
233 #[inline]
234 pub fn bit_is_set(&self) -> bool {
235 self.bit()
236 }
237}
238#[doc = r" Value of the field"]
239pub struct IOEV_AON_PROG0_ENR {
240 bits: bool,
241}
242impl IOEV_AON_PROG0_ENR {
243 #[doc = r" Value of the field as raw bits"]
244 #[inline]
245 pub fn bit(&self) -> bool {
246 self.bits
247 }
248 #[doc = r" Returns `true` if the bit is clear (0)"]
249 #[inline]
250 pub fn bit_is_clear(&self) -> bool {
251 !self.bit()
252 }
253 #[doc = r" Returns `true` if the bit is set (1)"]
254 #[inline]
255 pub fn bit_is_set(&self) -> bool {
256 self.bit()
257 }
258}
259#[doc = r" Value of the field"]
260pub struct RESERVED19R {
261 bits: u8,
262}
263impl RESERVED19R {
264 #[doc = r" Value of the field as raw bits"]
265 #[inline]
266 pub fn bits(&self) -> u8 {
267 self.bits
268 }
269}
270#[doc = r" Value of the field"]
271pub struct EDGE_IRQ_ENR {
272 bits: bool,
273}
274impl EDGE_IRQ_ENR {
275 #[doc = r" Value of the field as raw bits"]
276 #[inline]
277 pub fn bit(&self) -> bool {
278 self.bits
279 }
280 #[doc = r" Returns `true` if the bit is clear (0)"]
281 #[inline]
282 pub fn bit_is_clear(&self) -> bool {
283 !self.bit()
284 }
285 #[doc = r" Returns `true` if the bit is set (1)"]
286 #[inline]
287 pub fn bit_is_set(&self) -> bool {
288 self.bit()
289 }
290}
291#[doc = "Possible values of the field `EDGE_DET`"]
292#[derive(Clone, Copy, Debug, PartialEq)]
293pub enum EDGE_DETR {
294 #[doc = "Positive and negative edge detection"]
295 BOTH,
296 #[doc = "Positive edge detection"]
297 POS,
298 #[doc = "Negative edge detection"]
299 NEG,
300 #[doc = "No edge detection"]
301 NONE,
302}
303impl EDGE_DETR {
304 #[doc = r" Value of the field as raw bits"]
305 #[inline]
306 pub fn bits(&self) -> u8 {
307 match *self {
308 EDGE_DETR::BOTH => 3,
309 EDGE_DETR::POS => 2,
310 EDGE_DETR::NEG => 1,
311 EDGE_DETR::NONE => 0,
312 }
313 }
314 #[allow(missing_docs)]
315 #[doc(hidden)]
316 #[inline]
317 pub fn _from(value: u8) -> EDGE_DETR {
318 match value {
319 3 => EDGE_DETR::BOTH,
320 2 => EDGE_DETR::POS,
321 1 => EDGE_DETR::NEG,
322 0 => EDGE_DETR::NONE,
323 _ => unreachable!(),
324 }
325 }
326 #[doc = "Checks if the value of the field is `BOTH`"]
327 #[inline]
328 pub fn is_both(&self) -> bool {
329 *self == EDGE_DETR::BOTH
330 }
331 #[doc = "Checks if the value of the field is `POS`"]
332 #[inline]
333 pub fn is_pos(&self) -> bool {
334 *self == EDGE_DETR::POS
335 }
336 #[doc = "Checks if the value of the field is `NEG`"]
337 #[inline]
338 pub fn is_neg(&self) -> bool {
339 *self == EDGE_DETR::NEG
340 }
341 #[doc = "Checks if the value of the field is `NONE`"]
342 #[inline]
343 pub fn is_none(&self) -> bool {
344 *self == EDGE_DETR::NONE
345 }
346}
347#[doc = r" Value of the field"]
348pub struct RESERVED15R {
349 bits: bool,
350}
351impl RESERVED15R {
352 #[doc = r" Value of the field as raw bits"]
353 #[inline]
354 pub fn bit(&self) -> bool {
355 self.bits
356 }
357 #[doc = r" Returns `true` if the bit is clear (0)"]
358 #[inline]
359 pub fn bit_is_clear(&self) -> bool {
360 !self.bit()
361 }
362 #[doc = r" Returns `true` if the bit is set (1)"]
363 #[inline]
364 pub fn bit_is_set(&self) -> bool {
365 self.bit()
366 }
367}
368#[doc = "Possible values of the field `PULL_CTL`"]
369#[derive(Clone, Copy, Debug, PartialEq)]
370pub enum PULL_CTLR {
371 #[doc = "No pull"]
372 DIS,
373 #[doc = "Pull up"]
374 UP,
375 #[doc = "Pull down"]
376 DWN,
377 #[doc = r" Reserved"]
378 _Reserved(u8),
379}
380impl PULL_CTLR {
381 #[doc = r" Value of the field as raw bits"]
382 #[inline]
383 pub fn bits(&self) -> u8 {
384 match *self {
385 PULL_CTLR::DIS => 3,
386 PULL_CTLR::UP => 2,
387 PULL_CTLR::DWN => 1,
388 PULL_CTLR::_Reserved(bits) => bits,
389 }
390 }
391 #[allow(missing_docs)]
392 #[doc(hidden)]
393 #[inline]
394 pub fn _from(value: u8) -> PULL_CTLR {
395 match value {
396 3 => PULL_CTLR::DIS,
397 2 => PULL_CTLR::UP,
398 1 => PULL_CTLR::DWN,
399 i => PULL_CTLR::_Reserved(i),
400 }
401 }
402 #[doc = "Checks if the value of the field is `DIS`"]
403 #[inline]
404 pub fn is_dis(&self) -> bool {
405 *self == PULL_CTLR::DIS
406 }
407 #[doc = "Checks if the value of the field is `UP`"]
408 #[inline]
409 pub fn is_up(&self) -> bool {
410 *self == PULL_CTLR::UP
411 }
412 #[doc = "Checks if the value of the field is `DWN`"]
413 #[inline]
414 pub fn is_dwn(&self) -> bool {
415 *self == PULL_CTLR::DWN
416 }
417}
418#[doc = r" Value of the field"]
419pub struct SLEW_REDR {
420 bits: bool,
421}
422impl SLEW_REDR {
423 #[doc = r" Value of the field as raw bits"]
424 #[inline]
425 pub fn bit(&self) -> bool {
426 self.bits
427 }
428 #[doc = r" Returns `true` if the bit is clear (0)"]
429 #[inline]
430 pub fn bit_is_clear(&self) -> bool {
431 !self.bit()
432 }
433 #[doc = r" Returns `true` if the bit is set (1)"]
434 #[inline]
435 pub fn bit_is_set(&self) -> bool {
436 self.bit()
437 }
438}
439#[doc = "Possible values of the field `IOCURR`"]
440#[derive(Clone, Copy, Debug, PartialEq)]
441pub enum IOCURRR {
442 #[doc = "Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO"]
443 _4_8MA,
444 #[doc = "High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO"]
445 _4MA,
446 #[doc = "Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO"]
447 _2MA,
448 #[doc = r" Reserved"]
449 _Reserved(u8),
450}
451impl IOCURRR {
452 #[doc = r" Value of the field as raw bits"]
453 #[inline]
454 pub fn bits(&self) -> u8 {
455 match *self {
456 IOCURRR::_4_8MA => 2,
457 IOCURRR::_4MA => 1,
458 IOCURRR::_2MA => 0,
459 IOCURRR::_Reserved(bits) => bits,
460 }
461 }
462 #[allow(missing_docs)]
463 #[doc(hidden)]
464 #[inline]
465 pub fn _from(value: u8) -> IOCURRR {
466 match value {
467 2 => IOCURRR::_4_8MA,
468 1 => IOCURRR::_4MA,
469 0 => IOCURRR::_2MA,
470 i => IOCURRR::_Reserved(i),
471 }
472 }
473 #[doc = "Checks if the value of the field is `_4_8MA`"]
474 #[inline]
475 pub fn is_4_8ma(&self) -> bool {
476 *self == IOCURRR::_4_8MA
477 }
478 #[doc = "Checks if the value of the field is `_4MA`"]
479 #[inline]
480 pub fn is_4ma(&self) -> bool {
481 *self == IOCURRR::_4MA
482 }
483 #[doc = "Checks if the value of the field is `_2MA`"]
484 #[inline]
485 pub fn is_2ma(&self) -> bool {
486 *self == IOCURRR::_2MA
487 }
488}
489#[doc = "Possible values of the field `IOSTR`"]
490#[derive(Clone, Copy, Debug, PartialEq)]
491pub enum IOSTRR {
492 #[doc = "Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)"]
493 MAX,
494 #[doc = "Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)"]
495 MED,
496 #[doc = "Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)"]
497 MIN,
498 #[doc = "Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)"]
499 AUTO,
500}
501impl IOSTRR {
502 #[doc = r" Value of the field as raw bits"]
503 #[inline]
504 pub fn bits(&self) -> u8 {
505 match *self {
506 IOSTRR::MAX => 3,
507 IOSTRR::MED => 2,
508 IOSTRR::MIN => 1,
509 IOSTRR::AUTO => 0,
510 }
511 }
512 #[allow(missing_docs)]
513 #[doc(hidden)]
514 #[inline]
515 pub fn _from(value: u8) -> IOSTRR {
516 match value {
517 3 => IOSTRR::MAX,
518 2 => IOSTRR::MED,
519 1 => IOSTRR::MIN,
520 0 => IOSTRR::AUTO,
521 _ => unreachable!(),
522 }
523 }
524 #[doc = "Checks if the value of the field is `MAX`"]
525 #[inline]
526 pub fn is_max(&self) -> bool {
527 *self == IOSTRR::MAX
528 }
529 #[doc = "Checks if the value of the field is `MED`"]
530 #[inline]
531 pub fn is_med(&self) -> bool {
532 *self == IOSTRR::MED
533 }
534 #[doc = "Checks if the value of the field is `MIN`"]
535 #[inline]
536 pub fn is_min(&self) -> bool {
537 *self == IOSTRR::MIN
538 }
539 #[doc = "Checks if the value of the field is `AUTO`"]
540 #[inline]
541 pub fn is_auto(&self) -> bool {
542 *self == IOSTRR::AUTO
543 }
544}
545#[doc = r" Value of the field"]
546pub struct IOEV_RTC_ENR {
547 bits: bool,
548}
549impl IOEV_RTC_ENR {
550 #[doc = r" Value of the field as raw bits"]
551 #[inline]
552 pub fn bit(&self) -> bool {
553 self.bits
554 }
555 #[doc = r" Returns `true` if the bit is clear (0)"]
556 #[inline]
557 pub fn bit_is_clear(&self) -> bool {
558 !self.bit()
559 }
560 #[doc = r" Returns `true` if the bit is set (1)"]
561 #[inline]
562 pub fn bit_is_set(&self) -> bool {
563 self.bit()
564 }
565}
566#[doc = r" Value of the field"]
567pub struct IOEV_MCU_WU_ENR {
568 bits: bool,
569}
570impl IOEV_MCU_WU_ENR {
571 #[doc = r" Value of the field as raw bits"]
572 #[inline]
573 pub fn bit(&self) -> bool {
574 self.bits
575 }
576 #[doc = r" Returns `true` if the bit is clear (0)"]
577 #[inline]
578 pub fn bit_is_clear(&self) -> bool {
579 !self.bit()
580 }
581 #[doc = r" Returns `true` if the bit is set (1)"]
582 #[inline]
583 pub fn bit_is_set(&self) -> bool {
584 self.bit()
585 }
586}
587#[doc = "Possible values of the field `PORT_ID`"]
588#[derive(Clone, Copy, Debug, PartialEq)]
589pub enum PORT_IDR {
590 #[doc = "RF Core SMI Command Link In"]
591 RFC_SMI_CL_IN,
592 #[doc = "RF Core SMI Command Link Out"]
593 RFC_SMI_CL_OUT,
594 #[doc = "RF Core SMI Data Link In"]
595 RFC_SMI_DL_IN,
596 #[doc = "RF Core SMI Data Link Out"]
597 RFC_SMI_DL_OUT,
598 #[doc = "RF Core Data In 1"]
599 RFC_GPI1,
600 #[doc = "RF Core Data In 0"]
601 RFC_GPI0,
602 #[doc = "RF Core Data Out 3"]
603 RFC_GPO3,
604 #[doc = "RF Core Data Out 2"]
605 RFC_GPO2,
606 #[doc = "RF Core Data Out 1"]
607 RFC_GPO1,
608 #[doc = "RF Core Data Out 0"]
609 RFC_GPO0,
610 #[doc = "RF Core Trace"]
611 RFC_TRC,
612 #[doc = "I2S MCLK"]
613 I2S_MCLK,
614 #[doc = "I2S BCLK"]
615 I2S_BCLK,
616 #[doc = "I2S WCLK"]
617 I2S_WCLK,
618 #[doc = "I2S Data 1"]
619 I2S_AD1,
620 #[doc = "I2S Data 0"]
621 I2S_AD0,
622 #[doc = "SSI1 CLK"]
623 SSI1_CLK,
624 #[doc = "SSI1 FSS"]
625 SSI1_FSS,
626 #[doc = "SSI1 TX"]
627 SSI1_TX,
628 #[doc = "SSI1 RX"]
629 SSI1_RX,
630 #[doc = "CPU SWV"]
631 CPU_SWV,
632 #[doc = "PORT EVENT 7\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
633 PORT_EVENT7,
634 #[doc = "PORT EVENT 6\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
635 PORT_EVENT6,
636 #[doc = "PORT EVENT 5\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
637 PORT_EVENT5,
638 #[doc = "PORT EVENT 4\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
639 PORT_EVENT4,
640 #[doc = "PORT EVENT 3\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
641 PORT_EVENT3,
642 #[doc = "PORT EVENT 2\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
643 PORT_EVENT2,
644 #[doc = "PORT EVENT 1\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
645 PORT_EVENT1,
646 #[doc = "PORT EVENT 0\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
647 PORT_EVENT0,
648 #[doc = "UART1 RTS"]
649 UART1_RTS,
650 #[doc = "UART1 CTS"]
651 UART1_CTS,
652 #[doc = "UART1 TX"]
653 UART1_TX,
654 #[doc = "UART1 RX"]
655 UART1_RX,
656 #[doc = "UART0 RTS"]
657 UART0_RTS,
658 #[doc = "UART0 CTS"]
659 UART0_CTS,
660 #[doc = "UART0 TX"]
661 UART0_TX,
662 #[doc = "UART0 RX"]
663 UART0_RX,
664 #[doc = "I2C Clock"]
665 I2C_MSSCL,
666 #[doc = "I2C Data"]
667 I2C_MSSDA,
668 #[doc = "SSI0 CLK"]
669 SSI0_CLK,
670 #[doc = "SSI0 FSS"]
671 SSI0_FSS,
672 #[doc = "SSI0 TX"]
673 SSI0_TX,
674 #[doc = "SSI0 RX"]
675 SSI0_RX,
676 #[doc = "AUX IO"]
677 AUX_IO,
678 #[doc = "AON 32 KHz clock (SCLK_LF)"]
679 AON_CLK32K,
680 #[doc = "General Purpose IO"]
681 GPIO,
682 #[doc = r" Reserved"]
683 _Reserved(u8),
684}
685impl PORT_IDR {
686 #[doc = r" Value of the field as raw bits"]
687 #[inline]
688 pub fn bits(&self) -> u8 {
689 match *self {
690 PORT_IDR::RFC_SMI_CL_IN => 56,
691 PORT_IDR::RFC_SMI_CL_OUT => 55,
692 PORT_IDR::RFC_SMI_DL_IN => 54,
693 PORT_IDR::RFC_SMI_DL_OUT => 53,
694 PORT_IDR::RFC_GPI1 => 52,
695 PORT_IDR::RFC_GPI0 => 51,
696 PORT_IDR::RFC_GPO3 => 50,
697 PORT_IDR::RFC_GPO2 => 49,
698 PORT_IDR::RFC_GPO1 => 48,
699 PORT_IDR::RFC_GPO0 => 47,
700 PORT_IDR::RFC_TRC => 46,
701 PORT_IDR::I2S_MCLK => 41,
702 PORT_IDR::I2S_BCLK => 40,
703 PORT_IDR::I2S_WCLK => 39,
704 PORT_IDR::I2S_AD1 => 38,
705 PORT_IDR::I2S_AD0 => 37,
706 PORT_IDR::SSI1_CLK => 36,
707 PORT_IDR::SSI1_FSS => 35,
708 PORT_IDR::SSI1_TX => 34,
709 PORT_IDR::SSI1_RX => 33,
710 PORT_IDR::CPU_SWV => 32,
711 PORT_IDR::PORT_EVENT7 => 30,
712 PORT_IDR::PORT_EVENT6 => 29,
713 PORT_IDR::PORT_EVENT5 => 28,
714 PORT_IDR::PORT_EVENT4 => 27,
715 PORT_IDR::PORT_EVENT3 => 26,
716 PORT_IDR::PORT_EVENT2 => 25,
717 PORT_IDR::PORT_EVENT1 => 24,
718 PORT_IDR::PORT_EVENT0 => 23,
719 PORT_IDR::UART1_RTS => 22,
720 PORT_IDR::UART1_CTS => 21,
721 PORT_IDR::UART1_TX => 20,
722 PORT_IDR::UART1_RX => 19,
723 PORT_IDR::UART0_RTS => 18,
724 PORT_IDR::UART0_CTS => 17,
725 PORT_IDR::UART0_TX => 16,
726 PORT_IDR::UART0_RX => 15,
727 PORT_IDR::I2C_MSSCL => 14,
728 PORT_IDR::I2C_MSSDA => 13,
729 PORT_IDR::SSI0_CLK => 12,
730 PORT_IDR::SSI0_FSS => 11,
731 PORT_IDR::SSI0_TX => 10,
732 PORT_IDR::SSI0_RX => 9,
733 PORT_IDR::AUX_IO => 8,
734 PORT_IDR::AON_CLK32K => 7,
735 PORT_IDR::GPIO => 0,
736 PORT_IDR::_Reserved(bits) => bits,
737 }
738 }
739 #[allow(missing_docs)]
740 #[doc(hidden)]
741 #[inline]
742 pub fn _from(value: u8) -> PORT_IDR {
743 match value {
744 56 => PORT_IDR::RFC_SMI_CL_IN,
745 55 => PORT_IDR::RFC_SMI_CL_OUT,
746 54 => PORT_IDR::RFC_SMI_DL_IN,
747 53 => PORT_IDR::RFC_SMI_DL_OUT,
748 52 => PORT_IDR::RFC_GPI1,
749 51 => PORT_IDR::RFC_GPI0,
750 50 => PORT_IDR::RFC_GPO3,
751 49 => PORT_IDR::RFC_GPO2,
752 48 => PORT_IDR::RFC_GPO1,
753 47 => PORT_IDR::RFC_GPO0,
754 46 => PORT_IDR::RFC_TRC,
755 41 => PORT_IDR::I2S_MCLK,
756 40 => PORT_IDR::I2S_BCLK,
757 39 => PORT_IDR::I2S_WCLK,
758 38 => PORT_IDR::I2S_AD1,
759 37 => PORT_IDR::I2S_AD0,
760 36 => PORT_IDR::SSI1_CLK,
761 35 => PORT_IDR::SSI1_FSS,
762 34 => PORT_IDR::SSI1_TX,
763 33 => PORT_IDR::SSI1_RX,
764 32 => PORT_IDR::CPU_SWV,
765 30 => PORT_IDR::PORT_EVENT7,
766 29 => PORT_IDR::PORT_EVENT6,
767 28 => PORT_IDR::PORT_EVENT5,
768 27 => PORT_IDR::PORT_EVENT4,
769 26 => PORT_IDR::PORT_EVENT3,
770 25 => PORT_IDR::PORT_EVENT2,
771 24 => PORT_IDR::PORT_EVENT1,
772 23 => PORT_IDR::PORT_EVENT0,
773 22 => PORT_IDR::UART1_RTS,
774 21 => PORT_IDR::UART1_CTS,
775 20 => PORT_IDR::UART1_TX,
776 19 => PORT_IDR::UART1_RX,
777 18 => PORT_IDR::UART0_RTS,
778 17 => PORT_IDR::UART0_CTS,
779 16 => PORT_IDR::UART0_TX,
780 15 => PORT_IDR::UART0_RX,
781 14 => PORT_IDR::I2C_MSSCL,
782 13 => PORT_IDR::I2C_MSSDA,
783 12 => PORT_IDR::SSI0_CLK,
784 11 => PORT_IDR::SSI0_FSS,
785 10 => PORT_IDR::SSI0_TX,
786 9 => PORT_IDR::SSI0_RX,
787 8 => PORT_IDR::AUX_IO,
788 7 => PORT_IDR::AON_CLK32K,
789 0 => PORT_IDR::GPIO,
790 i => PORT_IDR::_Reserved(i),
791 }
792 }
793 #[doc = "Checks if the value of the field is `RFC_SMI_CL_IN`"]
794 #[inline]
795 pub fn is_rfc_smi_cl_in(&self) -> bool {
796 *self == PORT_IDR::RFC_SMI_CL_IN
797 }
798 #[doc = "Checks if the value of the field is `RFC_SMI_CL_OUT`"]
799 #[inline]
800 pub fn is_rfc_smi_cl_out(&self) -> bool {
801 *self == PORT_IDR::RFC_SMI_CL_OUT
802 }
803 #[doc = "Checks if the value of the field is `RFC_SMI_DL_IN`"]
804 #[inline]
805 pub fn is_rfc_smi_dl_in(&self) -> bool {
806 *self == PORT_IDR::RFC_SMI_DL_IN
807 }
808 #[doc = "Checks if the value of the field is `RFC_SMI_DL_OUT`"]
809 #[inline]
810 pub fn is_rfc_smi_dl_out(&self) -> bool {
811 *self == PORT_IDR::RFC_SMI_DL_OUT
812 }
813 #[doc = "Checks if the value of the field is `RFC_GPI1`"]
814 #[inline]
815 pub fn is_rfc_gpi1(&self) -> bool {
816 *self == PORT_IDR::RFC_GPI1
817 }
818 #[doc = "Checks if the value of the field is `RFC_GPI0`"]
819 #[inline]
820 pub fn is_rfc_gpi0(&self) -> bool {
821 *self == PORT_IDR::RFC_GPI0
822 }
823 #[doc = "Checks if the value of the field is `RFC_GPO3`"]
824 #[inline]
825 pub fn is_rfc_gpo3(&self) -> bool {
826 *self == PORT_IDR::RFC_GPO3
827 }
828 #[doc = "Checks if the value of the field is `RFC_GPO2`"]
829 #[inline]
830 pub fn is_rfc_gpo2(&self) -> bool {
831 *self == PORT_IDR::RFC_GPO2
832 }
833 #[doc = "Checks if the value of the field is `RFC_GPO1`"]
834 #[inline]
835 pub fn is_rfc_gpo1(&self) -> bool {
836 *self == PORT_IDR::RFC_GPO1
837 }
838 #[doc = "Checks if the value of the field is `RFC_GPO0`"]
839 #[inline]
840 pub fn is_rfc_gpo0(&self) -> bool {
841 *self == PORT_IDR::RFC_GPO0
842 }
843 #[doc = "Checks if the value of the field is `RFC_TRC`"]
844 #[inline]
845 pub fn is_rfc_trc(&self) -> bool {
846 *self == PORT_IDR::RFC_TRC
847 }
848 #[doc = "Checks if the value of the field is `I2S_MCLK`"]
849 #[inline]
850 pub fn is_i2s_mclk(&self) -> bool {
851 *self == PORT_IDR::I2S_MCLK
852 }
853 #[doc = "Checks if the value of the field is `I2S_BCLK`"]
854 #[inline]
855 pub fn is_i2s_bclk(&self) -> bool {
856 *self == PORT_IDR::I2S_BCLK
857 }
858 #[doc = "Checks if the value of the field is `I2S_WCLK`"]
859 #[inline]
860 pub fn is_i2s_wclk(&self) -> bool {
861 *self == PORT_IDR::I2S_WCLK
862 }
863 #[doc = "Checks if the value of the field is `I2S_AD1`"]
864 #[inline]
865 pub fn is_i2s_ad1(&self) -> bool {
866 *self == PORT_IDR::I2S_AD1
867 }
868 #[doc = "Checks if the value of the field is `I2S_AD0`"]
869 #[inline]
870 pub fn is_i2s_ad0(&self) -> bool {
871 *self == PORT_IDR::I2S_AD0
872 }
873 #[doc = "Checks if the value of the field is `SSI1_CLK`"]
874 #[inline]
875 pub fn is_ssi1_clk(&self) -> bool {
876 *self == PORT_IDR::SSI1_CLK
877 }
878 #[doc = "Checks if the value of the field is `SSI1_FSS`"]
879 #[inline]
880 pub fn is_ssi1_fss(&self) -> bool {
881 *self == PORT_IDR::SSI1_FSS
882 }
883 #[doc = "Checks if the value of the field is `SSI1_TX`"]
884 #[inline]
885 pub fn is_ssi1_tx(&self) -> bool {
886 *self == PORT_IDR::SSI1_TX
887 }
888 #[doc = "Checks if the value of the field is `SSI1_RX`"]
889 #[inline]
890 pub fn is_ssi1_rx(&self) -> bool {
891 *self == PORT_IDR::SSI1_RX
892 }
893 #[doc = "Checks if the value of the field is `CPU_SWV`"]
894 #[inline]
895 pub fn is_cpu_swv(&self) -> bool {
896 *self == PORT_IDR::CPU_SWV
897 }
898 #[doc = "Checks if the value of the field is `PORT_EVENT7`"]
899 #[inline]
900 pub fn is_port_event7(&self) -> bool {
901 *self == PORT_IDR::PORT_EVENT7
902 }
903 #[doc = "Checks if the value of the field is `PORT_EVENT6`"]
904 #[inline]
905 pub fn is_port_event6(&self) -> bool {
906 *self == PORT_IDR::PORT_EVENT6
907 }
908 #[doc = "Checks if the value of the field is `PORT_EVENT5`"]
909 #[inline]
910 pub fn is_port_event5(&self) -> bool {
911 *self == PORT_IDR::PORT_EVENT5
912 }
913 #[doc = "Checks if the value of the field is `PORT_EVENT4`"]
914 #[inline]
915 pub fn is_port_event4(&self) -> bool {
916 *self == PORT_IDR::PORT_EVENT4
917 }
918 #[doc = "Checks if the value of the field is `PORT_EVENT3`"]
919 #[inline]
920 pub fn is_port_event3(&self) -> bool {
921 *self == PORT_IDR::PORT_EVENT3
922 }
923 #[doc = "Checks if the value of the field is `PORT_EVENT2`"]
924 #[inline]
925 pub fn is_port_event2(&self) -> bool {
926 *self == PORT_IDR::PORT_EVENT2
927 }
928 #[doc = "Checks if the value of the field is `PORT_EVENT1`"]
929 #[inline]
930 pub fn is_port_event1(&self) -> bool {
931 *self == PORT_IDR::PORT_EVENT1
932 }
933 #[doc = "Checks if the value of the field is `PORT_EVENT0`"]
934 #[inline]
935 pub fn is_port_event0(&self) -> bool {
936 *self == PORT_IDR::PORT_EVENT0
937 }
938 #[doc = "Checks if the value of the field is `UART1_RTS`"]
939 #[inline]
940 pub fn is_uart1_rts(&self) -> bool {
941 *self == PORT_IDR::UART1_RTS
942 }
943 #[doc = "Checks if the value of the field is `UART1_CTS`"]
944 #[inline]
945 pub fn is_uart1_cts(&self) -> bool {
946 *self == PORT_IDR::UART1_CTS
947 }
948 #[doc = "Checks if the value of the field is `UART1_TX`"]
949 #[inline]
950 pub fn is_uart1_tx(&self) -> bool {
951 *self == PORT_IDR::UART1_TX
952 }
953 #[doc = "Checks if the value of the field is `UART1_RX`"]
954 #[inline]
955 pub fn is_uart1_rx(&self) -> bool {
956 *self == PORT_IDR::UART1_RX
957 }
958 #[doc = "Checks if the value of the field is `UART0_RTS`"]
959 #[inline]
960 pub fn is_uart0_rts(&self) -> bool {
961 *self == PORT_IDR::UART0_RTS
962 }
963 #[doc = "Checks if the value of the field is `UART0_CTS`"]
964 #[inline]
965 pub fn is_uart0_cts(&self) -> bool {
966 *self == PORT_IDR::UART0_CTS
967 }
968 #[doc = "Checks if the value of the field is `UART0_TX`"]
969 #[inline]
970 pub fn is_uart0_tx(&self) -> bool {
971 *self == PORT_IDR::UART0_TX
972 }
973 #[doc = "Checks if the value of the field is `UART0_RX`"]
974 #[inline]
975 pub fn is_uart0_rx(&self) -> bool {
976 *self == PORT_IDR::UART0_RX
977 }
978 #[doc = "Checks if the value of the field is `I2C_MSSCL`"]
979 #[inline]
980 pub fn is_i2c_msscl(&self) -> bool {
981 *self == PORT_IDR::I2C_MSSCL
982 }
983 #[doc = "Checks if the value of the field is `I2C_MSSDA`"]
984 #[inline]
985 pub fn is_i2c_mssda(&self) -> bool {
986 *self == PORT_IDR::I2C_MSSDA
987 }
988 #[doc = "Checks if the value of the field is `SSI0_CLK`"]
989 #[inline]
990 pub fn is_ssi0_clk(&self) -> bool {
991 *self == PORT_IDR::SSI0_CLK
992 }
993 #[doc = "Checks if the value of the field is `SSI0_FSS`"]
994 #[inline]
995 pub fn is_ssi0_fss(&self) -> bool {
996 *self == PORT_IDR::SSI0_FSS
997 }
998 #[doc = "Checks if the value of the field is `SSI0_TX`"]
999 #[inline]
1000 pub fn is_ssi0_tx(&self) -> bool {
1001 *self == PORT_IDR::SSI0_TX
1002 }
1003 #[doc = "Checks if the value of the field is `SSI0_RX`"]
1004 #[inline]
1005 pub fn is_ssi0_rx(&self) -> bool {
1006 *self == PORT_IDR::SSI0_RX
1007 }
1008 #[doc = "Checks if the value of the field is `AUX_IO`"]
1009 #[inline]
1010 pub fn is_aux_io(&self) -> bool {
1011 *self == PORT_IDR::AUX_IO
1012 }
1013 #[doc = "Checks if the value of the field is `AON_CLK32K`"]
1014 #[inline]
1015 pub fn is_aon_clk32k(&self) -> bool {
1016 *self == PORT_IDR::AON_CLK32K
1017 }
1018 #[doc = "Checks if the value of the field is `GPIO`"]
1019 #[inline]
1020 pub fn is_gpio(&self) -> bool {
1021 *self == PORT_IDR::GPIO
1022 }
1023}
1024#[doc = r" Proxy"]
1025pub struct _RESERVED31W<'a> {
1026 w: &'a mut W,
1027}
1028impl<'a> _RESERVED31W<'a> {
1029 #[doc = r" Sets the field bit"]
1030 pub fn set_bit(self) -> &'a mut W {
1031 self.bit(true)
1032 }
1033 #[doc = r" Clears the field bit"]
1034 pub fn clear_bit(self) -> &'a mut W {
1035 self.bit(false)
1036 }
1037 #[doc = r" Writes raw bits to the field"]
1038 #[inline]
1039 pub fn bit(self, value: bool) -> &'a mut W {
1040 const MASK: bool = true;
1041 const OFFSET: u8 = 31;
1042 self.w.bits &= !((MASK as u32) << OFFSET);
1043 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1044 self.w
1045 }
1046}
1047#[doc = r" Proxy"]
1048pub struct _HYST_ENW<'a> {
1049 w: &'a mut W,
1050}
1051impl<'a> _HYST_ENW<'a> {
1052 #[doc = r" Sets the field bit"]
1053 pub fn set_bit(self) -> &'a mut W {
1054 self.bit(true)
1055 }
1056 #[doc = r" Clears the field bit"]
1057 pub fn clear_bit(self) -> &'a mut W {
1058 self.bit(false)
1059 }
1060 #[doc = r" Writes raw bits to the field"]
1061 #[inline]
1062 pub fn bit(self, value: bool) -> &'a mut W {
1063 const MASK: bool = true;
1064 const OFFSET: u8 = 30;
1065 self.w.bits &= !((MASK as u32) << OFFSET);
1066 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1067 self.w
1068 }
1069}
1070#[doc = r" Proxy"]
1071pub struct _IEW<'a> {
1072 w: &'a mut W,
1073}
1074impl<'a> _IEW<'a> {
1075 #[doc = r" Sets the field bit"]
1076 pub fn set_bit(self) -> &'a mut W {
1077 self.bit(true)
1078 }
1079 #[doc = r" Clears the field bit"]
1080 pub fn clear_bit(self) -> &'a mut W {
1081 self.bit(false)
1082 }
1083 #[doc = r" Writes raw bits to the field"]
1084 #[inline]
1085 pub fn bit(self, value: bool) -> &'a mut W {
1086 const MASK: bool = true;
1087 const OFFSET: u8 = 29;
1088 self.w.bits &= !((MASK as u32) << OFFSET);
1089 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1090 self.w
1091 }
1092}
1093#[doc = r" Proxy"]
1094pub struct _WU_CFGW<'a> {
1095 w: &'a mut W,
1096}
1097impl<'a> _WU_CFGW<'a> {
1098 #[doc = r" Writes raw bits to the field"]
1099 #[inline]
1100 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1101 const MASK: u8 = 3;
1102 const OFFSET: u8 = 27;
1103 self.w.bits &= !((MASK as u32) << OFFSET);
1104 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1105 self.w
1106 }
1107}
1108#[doc = "Values that can be written to the field `IOMODE`"]
1109pub enum IOMODEW {
1110 #[doc = "Open Source\nInverted input / output"]
1111 OPENSRC_INV,
1112 #[doc = "Open Source\nNormal input / output"]
1113 OPENSRC,
1114 #[doc = "Open Drain\nInverted input / output"]
1115 OPENDR_INV,
1116 #[doc = "Open Drain, \nNormal input / output"]
1117 OPENDR,
1118 #[doc = "Inverted input / ouput"]
1119 INV,
1120 #[doc = "Normal input / output"]
1121 NORMAL,
1122}
1123impl IOMODEW {
1124 #[allow(missing_docs)]
1125 #[doc(hidden)]
1126 #[inline]
1127 pub fn _bits(&self) -> u8 {
1128 match *self {
1129 IOMODEW::OPENSRC_INV => 7,
1130 IOMODEW::OPENSRC => 6,
1131 IOMODEW::OPENDR_INV => 5,
1132 IOMODEW::OPENDR => 4,
1133 IOMODEW::INV => 1,
1134 IOMODEW::NORMAL => 0,
1135 }
1136 }
1137}
1138#[doc = r" Proxy"]
1139pub struct _IOMODEW<'a> {
1140 w: &'a mut W,
1141}
1142impl<'a> _IOMODEW<'a> {
1143 #[doc = r" Writes `variant` to the field"]
1144 #[inline]
1145 pub fn variant(self, variant: IOMODEW) -> &'a mut W {
1146 unsafe { self.bits(variant._bits()) }
1147 }
1148 #[doc = "Open Source Inverted input / output"]
1149 #[inline]
1150 pub fn opensrc_inv(self) -> &'a mut W {
1151 self.variant(IOMODEW::OPENSRC_INV)
1152 }
1153 #[doc = "Open Source Normal input / output"]
1154 #[inline]
1155 pub fn opensrc(self) -> &'a mut W {
1156 self.variant(IOMODEW::OPENSRC)
1157 }
1158 #[doc = "Open Drain Inverted input / output"]
1159 #[inline]
1160 pub fn opendr_inv(self) -> &'a mut W {
1161 self.variant(IOMODEW::OPENDR_INV)
1162 }
1163 #[doc = "Open Drain, Normal input / output"]
1164 #[inline]
1165 pub fn opendr(self) -> &'a mut W {
1166 self.variant(IOMODEW::OPENDR)
1167 }
1168 #[doc = "Inverted input / ouput"]
1169 #[inline]
1170 pub fn inv(self) -> &'a mut W {
1171 self.variant(IOMODEW::INV)
1172 }
1173 #[doc = "Normal input / output"]
1174 #[inline]
1175 pub fn normal(self) -> &'a mut W {
1176 self.variant(IOMODEW::NORMAL)
1177 }
1178 #[doc = r" Writes raw bits to the field"]
1179 #[inline]
1180 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1181 const MASK: u8 = 7;
1182 const OFFSET: u8 = 24;
1183 self.w.bits &= !((MASK as u32) << OFFSET);
1184 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1185 self.w
1186 }
1187}
1188#[doc = r" Proxy"]
1189pub struct _IOEV_AON_PROG2_ENW<'a> {
1190 w: &'a mut W,
1191}
1192impl<'a> _IOEV_AON_PROG2_ENW<'a> {
1193 #[doc = r" Sets the field bit"]
1194 pub fn set_bit(self) -> &'a mut W {
1195 self.bit(true)
1196 }
1197 #[doc = r" Clears the field bit"]
1198 pub fn clear_bit(self) -> &'a mut W {
1199 self.bit(false)
1200 }
1201 #[doc = r" Writes raw bits to the field"]
1202 #[inline]
1203 pub fn bit(self, value: bool) -> &'a mut W {
1204 const MASK: bool = true;
1205 const OFFSET: u8 = 23;
1206 self.w.bits &= !((MASK as u32) << OFFSET);
1207 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1208 self.w
1209 }
1210}
1211#[doc = r" Proxy"]
1212pub struct _IOEV_AON_PROG1_ENW<'a> {
1213 w: &'a mut W,
1214}
1215impl<'a> _IOEV_AON_PROG1_ENW<'a> {
1216 #[doc = r" Sets the field bit"]
1217 pub fn set_bit(self) -> &'a mut W {
1218 self.bit(true)
1219 }
1220 #[doc = r" Clears the field bit"]
1221 pub fn clear_bit(self) -> &'a mut W {
1222 self.bit(false)
1223 }
1224 #[doc = r" Writes raw bits to the field"]
1225 #[inline]
1226 pub fn bit(self, value: bool) -> &'a mut W {
1227 const MASK: bool = true;
1228 const OFFSET: u8 = 22;
1229 self.w.bits &= !((MASK as u32) << OFFSET);
1230 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1231 self.w
1232 }
1233}
1234#[doc = r" Proxy"]
1235pub struct _IOEV_AON_PROG0_ENW<'a> {
1236 w: &'a mut W,
1237}
1238impl<'a> _IOEV_AON_PROG0_ENW<'a> {
1239 #[doc = r" Sets the field bit"]
1240 pub fn set_bit(self) -> &'a mut W {
1241 self.bit(true)
1242 }
1243 #[doc = r" Clears the field bit"]
1244 pub fn clear_bit(self) -> &'a mut W {
1245 self.bit(false)
1246 }
1247 #[doc = r" Writes raw bits to the field"]
1248 #[inline]
1249 pub fn bit(self, value: bool) -> &'a mut W {
1250 const MASK: bool = true;
1251 const OFFSET: u8 = 21;
1252 self.w.bits &= !((MASK as u32) << OFFSET);
1253 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1254 self.w
1255 }
1256}
1257#[doc = r" Proxy"]
1258pub struct _RESERVED19W<'a> {
1259 w: &'a mut W,
1260}
1261impl<'a> _RESERVED19W<'a> {
1262 #[doc = r" Writes raw bits to the field"]
1263 #[inline]
1264 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1265 const MASK: u8 = 3;
1266 const OFFSET: u8 = 19;
1267 self.w.bits &= !((MASK as u32) << OFFSET);
1268 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1269 self.w
1270 }
1271}
1272#[doc = r" Proxy"]
1273pub struct _EDGE_IRQ_ENW<'a> {
1274 w: &'a mut W,
1275}
1276impl<'a> _EDGE_IRQ_ENW<'a> {
1277 #[doc = r" Sets the field bit"]
1278 pub fn set_bit(self) -> &'a mut W {
1279 self.bit(true)
1280 }
1281 #[doc = r" Clears the field bit"]
1282 pub fn clear_bit(self) -> &'a mut W {
1283 self.bit(false)
1284 }
1285 #[doc = r" Writes raw bits to the field"]
1286 #[inline]
1287 pub fn bit(self, value: bool) -> &'a mut W {
1288 const MASK: bool = true;
1289 const OFFSET: u8 = 18;
1290 self.w.bits &= !((MASK as u32) << OFFSET);
1291 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1292 self.w
1293 }
1294}
1295#[doc = "Values that can be written to the field `EDGE_DET`"]
1296pub enum EDGE_DETW {
1297 #[doc = "Positive and negative edge detection"]
1298 BOTH,
1299 #[doc = "Positive edge detection"]
1300 POS,
1301 #[doc = "Negative edge detection"]
1302 NEG,
1303 #[doc = "No edge detection"]
1304 NONE,
1305}
1306impl EDGE_DETW {
1307 #[allow(missing_docs)]
1308 #[doc(hidden)]
1309 #[inline]
1310 pub fn _bits(&self) -> u8 {
1311 match *self {
1312 EDGE_DETW::BOTH => 3,
1313 EDGE_DETW::POS => 2,
1314 EDGE_DETW::NEG => 1,
1315 EDGE_DETW::NONE => 0,
1316 }
1317 }
1318}
1319#[doc = r" Proxy"]
1320pub struct _EDGE_DETW<'a> {
1321 w: &'a mut W,
1322}
1323impl<'a> _EDGE_DETW<'a> {
1324 #[doc = r" Writes `variant` to the field"]
1325 #[inline]
1326 pub fn variant(self, variant: EDGE_DETW) -> &'a mut W {
1327 {
1328 self.bits(variant._bits())
1329 }
1330 }
1331 #[doc = "Positive and negative edge detection"]
1332 #[inline]
1333 pub fn both(self) -> &'a mut W {
1334 self.variant(EDGE_DETW::BOTH)
1335 }
1336 #[doc = "Positive edge detection"]
1337 #[inline]
1338 pub fn pos(self) -> &'a mut W {
1339 self.variant(EDGE_DETW::POS)
1340 }
1341 #[doc = "Negative edge detection"]
1342 #[inline]
1343 pub fn neg(self) -> &'a mut W {
1344 self.variant(EDGE_DETW::NEG)
1345 }
1346 #[doc = "No edge detection"]
1347 #[inline]
1348 pub fn none(self) -> &'a mut W {
1349 self.variant(EDGE_DETW::NONE)
1350 }
1351 #[doc = r" Writes raw bits to the field"]
1352 #[inline]
1353 pub fn bits(self, value: u8) -> &'a mut W {
1354 const MASK: u8 = 3;
1355 const OFFSET: u8 = 16;
1356 self.w.bits &= !((MASK as u32) << OFFSET);
1357 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1358 self.w
1359 }
1360}
1361#[doc = r" Proxy"]
1362pub struct _RESERVED15W<'a> {
1363 w: &'a mut W,
1364}
1365impl<'a> _RESERVED15W<'a> {
1366 #[doc = r" Sets the field bit"]
1367 pub fn set_bit(self) -> &'a mut W {
1368 self.bit(true)
1369 }
1370 #[doc = r" Clears the field bit"]
1371 pub fn clear_bit(self) -> &'a mut W {
1372 self.bit(false)
1373 }
1374 #[doc = r" Writes raw bits to the field"]
1375 #[inline]
1376 pub fn bit(self, value: bool) -> &'a mut W {
1377 const MASK: bool = true;
1378 const OFFSET: u8 = 15;
1379 self.w.bits &= !((MASK as u32) << OFFSET);
1380 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1381 self.w
1382 }
1383}
1384#[doc = "Values that can be written to the field `PULL_CTL`"]
1385pub enum PULL_CTLW {
1386 #[doc = "No pull"]
1387 DIS,
1388 #[doc = "Pull up"]
1389 UP,
1390 #[doc = "Pull down"]
1391 DWN,
1392}
1393impl PULL_CTLW {
1394 #[allow(missing_docs)]
1395 #[doc(hidden)]
1396 #[inline]
1397 pub fn _bits(&self) -> u8 {
1398 match *self {
1399 PULL_CTLW::DIS => 3,
1400 PULL_CTLW::UP => 2,
1401 PULL_CTLW::DWN => 1,
1402 }
1403 }
1404}
1405#[doc = r" Proxy"]
1406pub struct _PULL_CTLW<'a> {
1407 w: &'a mut W,
1408}
1409impl<'a> _PULL_CTLW<'a> {
1410 #[doc = r" Writes `variant` to the field"]
1411 #[inline]
1412 pub fn variant(self, variant: PULL_CTLW) -> &'a mut W {
1413 unsafe { self.bits(variant._bits()) }
1414 }
1415 #[doc = "No pull"]
1416 #[inline]
1417 pub fn dis(self) -> &'a mut W {
1418 self.variant(PULL_CTLW::DIS)
1419 }
1420 #[doc = "Pull up"]
1421 #[inline]
1422 pub fn up(self) -> &'a mut W {
1423 self.variant(PULL_CTLW::UP)
1424 }
1425 #[doc = "Pull down"]
1426 #[inline]
1427 pub fn dwn(self) -> &'a mut W {
1428 self.variant(PULL_CTLW::DWN)
1429 }
1430 #[doc = r" Writes raw bits to the field"]
1431 #[inline]
1432 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1433 const MASK: u8 = 3;
1434 const OFFSET: u8 = 13;
1435 self.w.bits &= !((MASK as u32) << OFFSET);
1436 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1437 self.w
1438 }
1439}
1440#[doc = r" Proxy"]
1441pub struct _SLEW_REDW<'a> {
1442 w: &'a mut W,
1443}
1444impl<'a> _SLEW_REDW<'a> {
1445 #[doc = r" Sets the field bit"]
1446 pub fn set_bit(self) -> &'a mut W {
1447 self.bit(true)
1448 }
1449 #[doc = r" Clears the field bit"]
1450 pub fn clear_bit(self) -> &'a mut W {
1451 self.bit(false)
1452 }
1453 #[doc = r" Writes raw bits to the field"]
1454 #[inline]
1455 pub fn bit(self, value: bool) -> &'a mut W {
1456 const MASK: bool = true;
1457 const OFFSET: u8 = 12;
1458 self.w.bits &= !((MASK as u32) << OFFSET);
1459 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1460 self.w
1461 }
1462}
1463#[doc = "Values that can be written to the field `IOCURR`"]
1464pub enum IOCURRW {
1465 #[doc = "Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO"]
1466 _4_8MA,
1467 #[doc = "High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO"]
1468 _4MA,
1469 #[doc = "Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO"]
1470 _2MA,
1471}
1472impl IOCURRW {
1473 #[allow(missing_docs)]
1474 #[doc(hidden)]
1475 #[inline]
1476 pub fn _bits(&self) -> u8 {
1477 match *self {
1478 IOCURRW::_4_8MA => 2,
1479 IOCURRW::_4MA => 1,
1480 IOCURRW::_2MA => 0,
1481 }
1482 }
1483}
1484#[doc = r" Proxy"]
1485pub struct _IOCURRW<'a> {
1486 w: &'a mut W,
1487}
1488impl<'a> _IOCURRW<'a> {
1489 #[doc = r" Writes `variant` to the field"]
1490 #[inline]
1491 pub fn variant(self, variant: IOCURRW) -> &'a mut W {
1492 unsafe { self.bits(variant._bits()) }
1493 }
1494 #[doc = "Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO"]
1495 #[inline]
1496 pub fn _4_8ma(self) -> &'a mut W {
1497 self.variant(IOCURRW::_4_8MA)
1498 }
1499 #[doc = "High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO"]
1500 #[inline]
1501 pub fn _4ma(self) -> &'a mut W {
1502 self.variant(IOCURRW::_4MA)
1503 }
1504 #[doc = "Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO"]
1505 #[inline]
1506 pub fn _2ma(self) -> &'a mut W {
1507 self.variant(IOCURRW::_2MA)
1508 }
1509 #[doc = r" Writes raw bits to the field"]
1510 #[inline]
1511 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1512 const MASK: u8 = 3;
1513 const OFFSET: u8 = 10;
1514 self.w.bits &= !((MASK as u32) << OFFSET);
1515 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1516 self.w
1517 }
1518}
1519#[doc = "Values that can be written to the field `IOSTR`"]
1520pub enum IOSTRW {
1521 #[doc = "Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)"]
1522 MAX,
1523 #[doc = "Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)"]
1524 MED,
1525 #[doc = "Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)"]
1526 MIN,
1527 #[doc = "Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)"]
1528 AUTO,
1529}
1530impl IOSTRW {
1531 #[allow(missing_docs)]
1532 #[doc(hidden)]
1533 #[inline]
1534 pub fn _bits(&self) -> u8 {
1535 match *self {
1536 IOSTRW::MAX => 3,
1537 IOSTRW::MED => 2,
1538 IOSTRW::MIN => 1,
1539 IOSTRW::AUTO => 0,
1540 }
1541 }
1542}
1543#[doc = r" Proxy"]
1544pub struct _IOSTRW<'a> {
1545 w: &'a mut W,
1546}
1547impl<'a> _IOSTRW<'a> {
1548 #[doc = r" Writes `variant` to the field"]
1549 #[inline]
1550 pub fn variant(self, variant: IOSTRW) -> &'a mut W {
1551 {
1552 self.bits(variant._bits())
1553 }
1554 }
1555 #[doc = "Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)"]
1556 #[inline]
1557 pub fn max(self) -> &'a mut W {
1558 self.variant(IOSTRW::MAX)
1559 }
1560 #[doc = "Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)"]
1561 #[inline]
1562 pub fn med(self) -> &'a mut W {
1563 self.variant(IOSTRW::MED)
1564 }
1565 #[doc = "Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)"]
1566 #[inline]
1567 pub fn min(self) -> &'a mut W {
1568 self.variant(IOSTRW::MIN)
1569 }
1570 #[doc = "Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)"]
1571 #[inline]
1572 pub fn auto(self) -> &'a mut W {
1573 self.variant(IOSTRW::AUTO)
1574 }
1575 #[doc = r" Writes raw bits to the field"]
1576 #[inline]
1577 pub fn bits(self, value: u8) -> &'a mut W {
1578 const MASK: u8 = 3;
1579 const OFFSET: u8 = 8;
1580 self.w.bits &= !((MASK as u32) << OFFSET);
1581 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1582 self.w
1583 }
1584}
1585#[doc = r" Proxy"]
1586pub struct _IOEV_RTC_ENW<'a> {
1587 w: &'a mut W,
1588}
1589impl<'a> _IOEV_RTC_ENW<'a> {
1590 #[doc = r" Sets the field bit"]
1591 pub fn set_bit(self) -> &'a mut W {
1592 self.bit(true)
1593 }
1594 #[doc = r" Clears the field bit"]
1595 pub fn clear_bit(self) -> &'a mut W {
1596 self.bit(false)
1597 }
1598 #[doc = r" Writes raw bits to the field"]
1599 #[inline]
1600 pub fn bit(self, value: bool) -> &'a mut W {
1601 const MASK: bool = true;
1602 const OFFSET: u8 = 7;
1603 self.w.bits &= !((MASK as u32) << OFFSET);
1604 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1605 self.w
1606 }
1607}
1608#[doc = r" Proxy"]
1609pub struct _IOEV_MCU_WU_ENW<'a> {
1610 w: &'a mut W,
1611}
1612impl<'a> _IOEV_MCU_WU_ENW<'a> {
1613 #[doc = r" Sets the field bit"]
1614 pub fn set_bit(self) -> &'a mut W {
1615 self.bit(true)
1616 }
1617 #[doc = r" Clears the field bit"]
1618 pub fn clear_bit(self) -> &'a mut W {
1619 self.bit(false)
1620 }
1621 #[doc = r" Writes raw bits to the field"]
1622 #[inline]
1623 pub fn bit(self, value: bool) -> &'a mut W {
1624 const MASK: bool = true;
1625 const OFFSET: u8 = 6;
1626 self.w.bits &= !((MASK as u32) << OFFSET);
1627 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1628 self.w
1629 }
1630}
1631#[doc = "Values that can be written to the field `PORT_ID`"]
1632pub enum PORT_IDW {
1633 #[doc = "RF Core SMI Command Link In"]
1634 RFC_SMI_CL_IN,
1635 #[doc = "RF Core SMI Command Link Out"]
1636 RFC_SMI_CL_OUT,
1637 #[doc = "RF Core SMI Data Link In"]
1638 RFC_SMI_DL_IN,
1639 #[doc = "RF Core SMI Data Link Out"]
1640 RFC_SMI_DL_OUT,
1641 #[doc = "RF Core Data In 1"]
1642 RFC_GPI1,
1643 #[doc = "RF Core Data In 0"]
1644 RFC_GPI0,
1645 #[doc = "RF Core Data Out 3"]
1646 RFC_GPO3,
1647 #[doc = "RF Core Data Out 2"]
1648 RFC_GPO2,
1649 #[doc = "RF Core Data Out 1"]
1650 RFC_GPO1,
1651 #[doc = "RF Core Data Out 0"]
1652 RFC_GPO0,
1653 #[doc = "RF Core Trace"]
1654 RFC_TRC,
1655 #[doc = "I2S MCLK"]
1656 I2S_MCLK,
1657 #[doc = "I2S BCLK"]
1658 I2S_BCLK,
1659 #[doc = "I2S WCLK"]
1660 I2S_WCLK,
1661 #[doc = "I2S Data 1"]
1662 I2S_AD1,
1663 #[doc = "I2S Data 0"]
1664 I2S_AD0,
1665 #[doc = "SSI1 CLK"]
1666 SSI1_CLK,
1667 #[doc = "SSI1 FSS"]
1668 SSI1_FSS,
1669 #[doc = "SSI1 TX"]
1670 SSI1_TX,
1671 #[doc = "SSI1 RX"]
1672 SSI1_RX,
1673 #[doc = "CPU SWV"]
1674 CPU_SWV,
1675 #[doc = "PORT EVENT 7\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1676 PORT_EVENT7,
1677 #[doc = "PORT EVENT 6\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1678 PORT_EVENT6,
1679 #[doc = "PORT EVENT 5\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1680 PORT_EVENT5,
1681 #[doc = "PORT EVENT 4\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1682 PORT_EVENT4,
1683 #[doc = "PORT EVENT 3\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1684 PORT_EVENT3,
1685 #[doc = "PORT EVENT 2\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1686 PORT_EVENT2,
1687 #[doc = "PORT EVENT 1\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1688 PORT_EVENT1,
1689 #[doc = "PORT EVENT 0\nCan be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1690 PORT_EVENT0,
1691 #[doc = "UART1 RTS"]
1692 UART1_RTS,
1693 #[doc = "UART1 CTS"]
1694 UART1_CTS,
1695 #[doc = "UART1 TX"]
1696 UART1_TX,
1697 #[doc = "UART1 RX"]
1698 UART1_RX,
1699 #[doc = "UART0 RTS"]
1700 UART0_RTS,
1701 #[doc = "UART0 CTS"]
1702 UART0_CTS,
1703 #[doc = "UART0 TX"]
1704 UART0_TX,
1705 #[doc = "UART0 RX"]
1706 UART0_RX,
1707 #[doc = "I2C Clock"]
1708 I2C_MSSCL,
1709 #[doc = "I2C Data"]
1710 I2C_MSSDA,
1711 #[doc = "SSI0 CLK"]
1712 SSI0_CLK,
1713 #[doc = "SSI0 FSS"]
1714 SSI0_FSS,
1715 #[doc = "SSI0 TX"]
1716 SSI0_TX,
1717 #[doc = "SSI0 RX"]
1718 SSI0_RX,
1719 #[doc = "AUX IO"]
1720 AUX_IO,
1721 #[doc = "AON 32 KHz clock (SCLK_LF)"]
1722 AON_CLK32K,
1723 #[doc = "General Purpose IO"]
1724 GPIO,
1725}
1726impl PORT_IDW {
1727 #[allow(missing_docs)]
1728 #[doc(hidden)]
1729 #[inline]
1730 pub fn _bits(&self) -> u8 {
1731 match *self {
1732 PORT_IDW::RFC_SMI_CL_IN => 56,
1733 PORT_IDW::RFC_SMI_CL_OUT => 55,
1734 PORT_IDW::RFC_SMI_DL_IN => 54,
1735 PORT_IDW::RFC_SMI_DL_OUT => 53,
1736 PORT_IDW::RFC_GPI1 => 52,
1737 PORT_IDW::RFC_GPI0 => 51,
1738 PORT_IDW::RFC_GPO3 => 50,
1739 PORT_IDW::RFC_GPO2 => 49,
1740 PORT_IDW::RFC_GPO1 => 48,
1741 PORT_IDW::RFC_GPO0 => 47,
1742 PORT_IDW::RFC_TRC => 46,
1743 PORT_IDW::I2S_MCLK => 41,
1744 PORT_IDW::I2S_BCLK => 40,
1745 PORT_IDW::I2S_WCLK => 39,
1746 PORT_IDW::I2S_AD1 => 38,
1747 PORT_IDW::I2S_AD0 => 37,
1748 PORT_IDW::SSI1_CLK => 36,
1749 PORT_IDW::SSI1_FSS => 35,
1750 PORT_IDW::SSI1_TX => 34,
1751 PORT_IDW::SSI1_RX => 33,
1752 PORT_IDW::CPU_SWV => 32,
1753 PORT_IDW::PORT_EVENT7 => 30,
1754 PORT_IDW::PORT_EVENT6 => 29,
1755 PORT_IDW::PORT_EVENT5 => 28,
1756 PORT_IDW::PORT_EVENT4 => 27,
1757 PORT_IDW::PORT_EVENT3 => 26,
1758 PORT_IDW::PORT_EVENT2 => 25,
1759 PORT_IDW::PORT_EVENT1 => 24,
1760 PORT_IDW::PORT_EVENT0 => 23,
1761 PORT_IDW::UART1_RTS => 22,
1762 PORT_IDW::UART1_CTS => 21,
1763 PORT_IDW::UART1_TX => 20,
1764 PORT_IDW::UART1_RX => 19,
1765 PORT_IDW::UART0_RTS => 18,
1766 PORT_IDW::UART0_CTS => 17,
1767 PORT_IDW::UART0_TX => 16,
1768 PORT_IDW::UART0_RX => 15,
1769 PORT_IDW::I2C_MSSCL => 14,
1770 PORT_IDW::I2C_MSSDA => 13,
1771 PORT_IDW::SSI0_CLK => 12,
1772 PORT_IDW::SSI0_FSS => 11,
1773 PORT_IDW::SSI0_TX => 10,
1774 PORT_IDW::SSI0_RX => 9,
1775 PORT_IDW::AUX_IO => 8,
1776 PORT_IDW::AON_CLK32K => 7,
1777 PORT_IDW::GPIO => 0,
1778 }
1779 }
1780}
1781#[doc = r" Proxy"]
1782pub struct _PORT_IDW<'a> {
1783 w: &'a mut W,
1784}
1785impl<'a> _PORT_IDW<'a> {
1786 #[doc = r" Writes `variant` to the field"]
1787 #[inline]
1788 pub fn variant(self, variant: PORT_IDW) -> &'a mut W {
1789 unsafe { self.bits(variant._bits()) }
1790 }
1791 #[doc = "RF Core SMI Command Link In"]
1792 #[inline]
1793 pub fn rfc_smi_cl_in(self) -> &'a mut W {
1794 self.variant(PORT_IDW::RFC_SMI_CL_IN)
1795 }
1796 #[doc = "RF Core SMI Command Link Out"]
1797 #[inline]
1798 pub fn rfc_smi_cl_out(self) -> &'a mut W {
1799 self.variant(PORT_IDW::RFC_SMI_CL_OUT)
1800 }
1801 #[doc = "RF Core SMI Data Link In"]
1802 #[inline]
1803 pub fn rfc_smi_dl_in(self) -> &'a mut W {
1804 self.variant(PORT_IDW::RFC_SMI_DL_IN)
1805 }
1806 #[doc = "RF Core SMI Data Link Out"]
1807 #[inline]
1808 pub fn rfc_smi_dl_out(self) -> &'a mut W {
1809 self.variant(PORT_IDW::RFC_SMI_DL_OUT)
1810 }
1811 #[doc = "RF Core Data In 1"]
1812 #[inline]
1813 pub fn rfc_gpi1(self) -> &'a mut W {
1814 self.variant(PORT_IDW::RFC_GPI1)
1815 }
1816 #[doc = "RF Core Data In 0"]
1817 #[inline]
1818 pub fn rfc_gpi0(self) -> &'a mut W {
1819 self.variant(PORT_IDW::RFC_GPI0)
1820 }
1821 #[doc = "RF Core Data Out 3"]
1822 #[inline]
1823 pub fn rfc_gpo3(self) -> &'a mut W {
1824 self.variant(PORT_IDW::RFC_GPO3)
1825 }
1826 #[doc = "RF Core Data Out 2"]
1827 #[inline]
1828 pub fn rfc_gpo2(self) -> &'a mut W {
1829 self.variant(PORT_IDW::RFC_GPO2)
1830 }
1831 #[doc = "RF Core Data Out 1"]
1832 #[inline]
1833 pub fn rfc_gpo1(self) -> &'a mut W {
1834 self.variant(PORT_IDW::RFC_GPO1)
1835 }
1836 #[doc = "RF Core Data Out 0"]
1837 #[inline]
1838 pub fn rfc_gpo0(self) -> &'a mut W {
1839 self.variant(PORT_IDW::RFC_GPO0)
1840 }
1841 #[doc = "RF Core Trace"]
1842 #[inline]
1843 pub fn rfc_trc(self) -> &'a mut W {
1844 self.variant(PORT_IDW::RFC_TRC)
1845 }
1846 #[doc = "I2S MCLK"]
1847 #[inline]
1848 pub fn i2s_mclk(self) -> &'a mut W {
1849 self.variant(PORT_IDW::I2S_MCLK)
1850 }
1851 #[doc = "I2S BCLK"]
1852 #[inline]
1853 pub fn i2s_bclk(self) -> &'a mut W {
1854 self.variant(PORT_IDW::I2S_BCLK)
1855 }
1856 #[doc = "I2S WCLK"]
1857 #[inline]
1858 pub fn i2s_wclk(self) -> &'a mut W {
1859 self.variant(PORT_IDW::I2S_WCLK)
1860 }
1861 #[doc = "I2S Data 1"]
1862 #[inline]
1863 pub fn i2s_ad1(self) -> &'a mut W {
1864 self.variant(PORT_IDW::I2S_AD1)
1865 }
1866 #[doc = "I2S Data 0"]
1867 #[inline]
1868 pub fn i2s_ad0(self) -> &'a mut W {
1869 self.variant(PORT_IDW::I2S_AD0)
1870 }
1871 #[doc = "SSI1 CLK"]
1872 #[inline]
1873 pub fn ssi1_clk(self) -> &'a mut W {
1874 self.variant(PORT_IDW::SSI1_CLK)
1875 }
1876 #[doc = "SSI1 FSS"]
1877 #[inline]
1878 pub fn ssi1_fss(self) -> &'a mut W {
1879 self.variant(PORT_IDW::SSI1_FSS)
1880 }
1881 #[doc = "SSI1 TX"]
1882 #[inline]
1883 pub fn ssi1_tx(self) -> &'a mut W {
1884 self.variant(PORT_IDW::SSI1_TX)
1885 }
1886 #[doc = "SSI1 RX"]
1887 #[inline]
1888 pub fn ssi1_rx(self) -> &'a mut W {
1889 self.variant(PORT_IDW::SSI1_RX)
1890 }
1891 #[doc = "CPU SWV"]
1892 #[inline]
1893 pub fn cpu_swv(self) -> &'a mut W {
1894 self.variant(PORT_IDW::CPU_SWV)
1895 }
1896 #[doc = "PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1897 #[inline]
1898 pub fn port_event7(self) -> &'a mut W {
1899 self.variant(PORT_IDW::PORT_EVENT7)
1900 }
1901 #[doc = "PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1902 #[inline]
1903 pub fn port_event6(self) -> &'a mut W {
1904 self.variant(PORT_IDW::PORT_EVENT6)
1905 }
1906 #[doc = "PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1907 #[inline]
1908 pub fn port_event5(self) -> &'a mut W {
1909 self.variant(PORT_IDW::PORT_EVENT5)
1910 }
1911 #[doc = "PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1912 #[inline]
1913 pub fn port_event4(self) -> &'a mut W {
1914 self.variant(PORT_IDW::PORT_EVENT4)
1915 }
1916 #[doc = "PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1917 #[inline]
1918 pub fn port_event3(self) -> &'a mut W {
1919 self.variant(PORT_IDW::PORT_EVENT3)
1920 }
1921 #[doc = "PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1922 #[inline]
1923 pub fn port_event2(self) -> &'a mut W {
1924 self.variant(PORT_IDW::PORT_EVENT2)
1925 }
1926 #[doc = "PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1927 #[inline]
1928 pub fn port_event1(self) -> &'a mut W {
1929 self.variant(PORT_IDW::PORT_EVENT1)
1930 }
1931 #[doc = "PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on"]
1932 #[inline]
1933 pub fn port_event0(self) -> &'a mut W {
1934 self.variant(PORT_IDW::PORT_EVENT0)
1935 }
1936 #[doc = "UART1 RTS"]
1937 #[inline]
1938 pub fn uart1_rts(self) -> &'a mut W {
1939 self.variant(PORT_IDW::UART1_RTS)
1940 }
1941 #[doc = "UART1 CTS"]
1942 #[inline]
1943 pub fn uart1_cts(self) -> &'a mut W {
1944 self.variant(PORT_IDW::UART1_CTS)
1945 }
1946 #[doc = "UART1 TX"]
1947 #[inline]
1948 pub fn uart1_tx(self) -> &'a mut W {
1949 self.variant(PORT_IDW::UART1_TX)
1950 }
1951 #[doc = "UART1 RX"]
1952 #[inline]
1953 pub fn uart1_rx(self) -> &'a mut W {
1954 self.variant(PORT_IDW::UART1_RX)
1955 }
1956 #[doc = "UART0 RTS"]
1957 #[inline]
1958 pub fn uart0_rts(self) -> &'a mut W {
1959 self.variant(PORT_IDW::UART0_RTS)
1960 }
1961 #[doc = "UART0 CTS"]
1962 #[inline]
1963 pub fn uart0_cts(self) -> &'a mut W {
1964 self.variant(PORT_IDW::UART0_CTS)
1965 }
1966 #[doc = "UART0 TX"]
1967 #[inline]
1968 pub fn uart0_tx(self) -> &'a mut W {
1969 self.variant(PORT_IDW::UART0_TX)
1970 }
1971 #[doc = "UART0 RX"]
1972 #[inline]
1973 pub fn uart0_rx(self) -> &'a mut W {
1974 self.variant(PORT_IDW::UART0_RX)
1975 }
1976 #[doc = "I2C Clock"]
1977 #[inline]
1978 pub fn i2c_msscl(self) -> &'a mut W {
1979 self.variant(PORT_IDW::I2C_MSSCL)
1980 }
1981 #[doc = "I2C Data"]
1982 #[inline]
1983 pub fn i2c_mssda(self) -> &'a mut W {
1984 self.variant(PORT_IDW::I2C_MSSDA)
1985 }
1986 #[doc = "SSI0 CLK"]
1987 #[inline]
1988 pub fn ssi0_clk(self) -> &'a mut W {
1989 self.variant(PORT_IDW::SSI0_CLK)
1990 }
1991 #[doc = "SSI0 FSS"]
1992 #[inline]
1993 pub fn ssi0_fss(self) -> &'a mut W {
1994 self.variant(PORT_IDW::SSI0_FSS)
1995 }
1996 #[doc = "SSI0 TX"]
1997 #[inline]
1998 pub fn ssi0_tx(self) -> &'a mut W {
1999 self.variant(PORT_IDW::SSI0_TX)
2000 }
2001 #[doc = "SSI0 RX"]
2002 #[inline]
2003 pub fn ssi0_rx(self) -> &'a mut W {
2004 self.variant(PORT_IDW::SSI0_RX)
2005 }
2006 #[doc = "AUX IO"]
2007 #[inline]
2008 pub fn aux_io(self) -> &'a mut W {
2009 self.variant(PORT_IDW::AUX_IO)
2010 }
2011 #[doc = "AON 32 KHz clock (SCLK_LF)"]
2012 #[inline]
2013 pub fn aon_clk32k(self) -> &'a mut W {
2014 self.variant(PORT_IDW::AON_CLK32K)
2015 }
2016 #[doc = "General Purpose IO"]
2017 #[inline]
2018 pub fn gpio(self) -> &'a mut W {
2019 self.variant(PORT_IDW::GPIO)
2020 }
2021 #[doc = r" Writes raw bits to the field"]
2022 #[inline]
2023 pub unsafe fn bits(self, value: u8) -> &'a mut W {
2024 const MASK: u8 = 63;
2025 const OFFSET: u8 = 0;
2026 self.w.bits &= !((MASK as u32) << OFFSET);
2027 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2028 self.w
2029 }
2030}
2031impl R {
2032 #[doc = r" Value of the register as raw bits"]
2033 #[inline]
2034 pub fn bits(&self) -> u32 {
2035 self.bits
2036 }
2037 #[doc = "Bit 31 - 31:31\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
2038 #[inline]
2039 pub fn reserved31(&self) -> RESERVED31R {
2040 let bits = {
2041 const MASK: bool = true;
2042 const OFFSET: u8 = 31;
2043 ((self.bits >> OFFSET) & MASK as u32) != 0
2044 };
2045 RESERVED31R { bits }
2046 }
2047 #[doc = "Bit 30 - 30:30\\] 0: Input hysteresis disable 1: Input hysteresis enable"]
2048 #[inline]
2049 pub fn hyst_en(&self) -> HYST_ENR {
2050 let bits = {
2051 const MASK: bool = true;
2052 const OFFSET: u8 = 30;
2053 ((self.bits >> OFFSET) & MASK as u32) != 0
2054 };
2055 HYST_ENR { bits }
2056 }
2057 #[doc = "Bit 29 - 29:29\\] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored."]
2058 #[inline]
2059 pub fn ie(&self) -> IER {
2060 let bits = {
2061 const MASK: bool = true;
2062 const OFFSET: u8 = 29;
2063 ((self.bits >> OFFSET) & MASK as u32) != 0
2064 };
2065 IER { bits }
2066 }
2067 #[doc = "Bits 27:28 - 28:27\\] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO."]
2068 #[inline]
2069 pub fn wu_cfg(&self) -> WU_CFGR {
2070 let bits = {
2071 const MASK: u8 = 3;
2072 const OFFSET: u8 = 27;
2073 ((self.bits >> OFFSET) & MASK as u32) as u8
2074 };
2075 WU_CFGR { bits }
2076 }
2077 #[doc = "Bits 24:26 - 26:24\\] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior."]
2078 #[inline]
2079 pub fn iomode(&self) -> IOMODER {
2080 IOMODER::_from({
2081 const MASK: u8 = 7;
2082 const OFFSET: u8 = 24;
2083 ((self.bits >> OFFSET) & MASK as u32) as u8
2084 })
2085 }
2086 #[doc = "Bit 23 - 23:23\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event"]
2087 #[inline]
2088 pub fn ioev_aon_prog2_en(&self) -> IOEV_AON_PROG2_ENR {
2089 let bits = {
2090 const MASK: bool = true;
2091 const OFFSET: u8 = 23;
2092 ((self.bits >> OFFSET) & MASK as u32) != 0
2093 };
2094 IOEV_AON_PROG2_ENR { bits }
2095 }
2096 #[doc = "Bit 22 - 22:22\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event"]
2097 #[inline]
2098 pub fn ioev_aon_prog1_en(&self) -> IOEV_AON_PROG1_ENR {
2099 let bits = {
2100 const MASK: bool = true;
2101 const OFFSET: u8 = 22;
2102 ((self.bits >> OFFSET) & MASK as u32) != 0
2103 };
2104 IOEV_AON_PROG1_ENR { bits }
2105 }
2106 #[doc = "Bit 21 - 21:21\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event"]
2107 #[inline]
2108 pub fn ioev_aon_prog0_en(&self) -> IOEV_AON_PROG0_ENR {
2109 let bits = {
2110 const MASK: bool = true;
2111 const OFFSET: u8 = 21;
2112 ((self.bits >> OFFSET) & MASK as u32) != 0
2113 };
2114 IOEV_AON_PROG0_ENR { bits }
2115 }
2116 #[doc = "Bits 19:20 - 20:19\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
2117 #[inline]
2118 pub fn reserved19(&self) -> RESERVED19R {
2119 let bits = {
2120 const MASK: u8 = 3;
2121 const OFFSET: u8 = 19;
2122 ((self.bits >> OFFSET) & MASK as u32) as u8
2123 };
2124 RESERVED19R { bits }
2125 }
2126 #[doc = "Bit 18 - 18:18\\] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)"]
2127 #[inline]
2128 pub fn edge_irq_en(&self) -> EDGE_IRQ_ENR {
2129 let bits = {
2130 const MASK: bool = true;
2131 const OFFSET: u8 = 18;
2132 ((self.bits >> OFFSET) & MASK as u32) != 0
2133 };
2134 EDGE_IRQ_ENR { bits }
2135 }
2136 #[doc = "Bits 16:17 - 17:16\\] Enable generation of edge detection events on this IO"]
2137 #[inline]
2138 pub fn edge_det(&self) -> EDGE_DETR {
2139 EDGE_DETR::_from({
2140 const MASK: u8 = 3;
2141 const OFFSET: u8 = 16;
2142 ((self.bits >> OFFSET) & MASK as u32) as u8
2143 })
2144 }
2145 #[doc = "Bit 15 - 15:15\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
2146 #[inline]
2147 pub fn reserved15(&self) -> RESERVED15R {
2148 let bits = {
2149 const MASK: bool = true;
2150 const OFFSET: u8 = 15;
2151 ((self.bits >> OFFSET) & MASK as u32) != 0
2152 };
2153 RESERVED15R { bits }
2154 }
2155 #[doc = "Bits 13:14 - 14:13\\] Pull control"]
2156 #[inline]
2157 pub fn pull_ctl(&self) -> PULL_CTLR {
2158 PULL_CTLR::_from({
2159 const MASK: u8 = 3;
2160 const OFFSET: u8 = 13;
2161 ((self.bits >> OFFSET) & MASK as u32) as u8
2162 })
2163 }
2164 #[doc = "Bit 12 - 12:12\\] 0: Normal slew rate 1: Enables reduced slew rate in output driver."]
2165 #[inline]
2166 pub fn slew_red(&self) -> SLEW_REDR {
2167 let bits = {
2168 const MASK: bool = true;
2169 const OFFSET: u8 = 12;
2170 ((self.bits >> OFFSET) & MASK as u32) != 0
2171 };
2172 SLEW_REDR { bits }
2173 }
2174 #[doc = "Bits 10:11 - 11:10\\] Selects IO current mode of this IO."]
2175 #[inline]
2176 pub fn iocurr(&self) -> IOCURRR {
2177 IOCURRR::_from({
2178 const MASK: u8 = 3;
2179 const OFFSET: u8 = 10;
2180 ((self.bits >> OFFSET) & MASK as u32) as u8
2181 })
2182 }
2183 #[doc = "Bits 8:9 - 9:8\\] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR"]
2184 #[inline]
2185 pub fn iostr(&self) -> IOSTRR {
2186 IOSTRR::_from({
2187 const MASK: u8 = 3;
2188 const OFFSET: u8 = 8;
2189 ((self.bits >> OFFSET) & MASK as u32) as u8
2190 })
2191 }
2192 #[doc = "Bit 7 - 7:7\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event"]
2193 #[inline]
2194 pub fn ioev_rtc_en(&self) -> IOEV_RTC_ENR {
2195 let bits = {
2196 const MASK: bool = true;
2197 const OFFSET: u8 = 7;
2198 ((self.bits >> OFFSET) & MASK as u32) != 0
2199 };
2200 IOEV_RTC_ENR { bits }
2201 }
2202 #[doc = "Bit 6 - 6:6\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event"]
2203 #[inline]
2204 pub fn ioev_mcu_wu_en(&self) -> IOEV_MCU_WU_ENR {
2205 let bits = {
2206 const MASK: bool = true;
2207 const OFFSET: u8 = 6;
2208 ((self.bits >> OFFSET) & MASK as u32) != 0
2209 };
2210 IOEV_MCU_WU_ENR { bits }
2211 }
2212 #[doc = "Bits 0:5 - 5:0\\] Selects usage for DIO5"]
2213 #[inline]
2214 pub fn port_id(&self) -> PORT_IDR {
2215 PORT_IDR::_from({
2216 const MASK: u8 = 63;
2217 const OFFSET: u8 = 0;
2218 ((self.bits >> OFFSET) & MASK as u32) as u8
2219 })
2220 }
2221}
2222impl W {
2223 #[doc = r" Reset value of the register"]
2224 #[inline]
2225 pub fn reset_value() -> W {
2226 W { bits: 24576 }
2227 }
2228 #[doc = r" Writes raw bits to the register"]
2229 #[inline]
2230 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2231 self.bits = bits;
2232 self
2233 }
2234 #[doc = "Bit 31 - 31:31\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
2235 #[inline]
2236 pub fn reserved31(&mut self) -> _RESERVED31W {
2237 _RESERVED31W { w: self }
2238 }
2239 #[doc = "Bit 30 - 30:30\\] 0: Input hysteresis disable 1: Input hysteresis enable"]
2240 #[inline]
2241 pub fn hyst_en(&mut self) -> _HYST_ENW {
2242 _HYST_ENW { w: self }
2243 }
2244 #[doc = "Bit 29 - 29:29\\] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored."]
2245 #[inline]
2246 pub fn ie(&mut self) -> _IEW {
2247 _IEW { w: self }
2248 }
2249 #[doc = "Bits 27:28 - 28:27\\] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO."]
2250 #[inline]
2251 pub fn wu_cfg(&mut self) -> _WU_CFGW {
2252 _WU_CFGW { w: self }
2253 }
2254 #[doc = "Bits 24:26 - 26:24\\] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior."]
2255 #[inline]
2256 pub fn iomode(&mut self) -> _IOMODEW {
2257 _IOMODEW { w: self }
2258 }
2259 #[doc = "Bit 23 - 23:23\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event"]
2260 #[inline]
2261 pub fn ioev_aon_prog2_en(&mut self) -> _IOEV_AON_PROG2_ENW {
2262 _IOEV_AON_PROG2_ENW { w: self }
2263 }
2264 #[doc = "Bit 22 - 22:22\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event"]
2265 #[inline]
2266 pub fn ioev_aon_prog1_en(&mut self) -> _IOEV_AON_PROG1_ENW {
2267 _IOEV_AON_PROG1_ENW { w: self }
2268 }
2269 #[doc = "Bit 21 - 21:21\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event"]
2270 #[inline]
2271 pub fn ioev_aon_prog0_en(&mut self) -> _IOEV_AON_PROG0_ENW {
2272 _IOEV_AON_PROG0_ENW { w: self }
2273 }
2274 #[doc = "Bits 19:20 - 20:19\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
2275 #[inline]
2276 pub fn reserved19(&mut self) -> _RESERVED19W {
2277 _RESERVED19W { w: self }
2278 }
2279 #[doc = "Bit 18 - 18:18\\] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)"]
2280 #[inline]
2281 pub fn edge_irq_en(&mut self) -> _EDGE_IRQ_ENW {
2282 _EDGE_IRQ_ENW { w: self }
2283 }
2284 #[doc = "Bits 16:17 - 17:16\\] Enable generation of edge detection events on this IO"]
2285 #[inline]
2286 pub fn edge_det(&mut self) -> _EDGE_DETW {
2287 _EDGE_DETW { w: self }
2288 }
2289 #[doc = "Bit 15 - 15:15\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
2290 #[inline]
2291 pub fn reserved15(&mut self) -> _RESERVED15W {
2292 _RESERVED15W { w: self }
2293 }
2294 #[doc = "Bits 13:14 - 14:13\\] Pull control"]
2295 #[inline]
2296 pub fn pull_ctl(&mut self) -> _PULL_CTLW {
2297 _PULL_CTLW { w: self }
2298 }
2299 #[doc = "Bit 12 - 12:12\\] 0: Normal slew rate 1: Enables reduced slew rate in output driver."]
2300 #[inline]
2301 pub fn slew_red(&mut self) -> _SLEW_REDW {
2302 _SLEW_REDW { w: self }
2303 }
2304 #[doc = "Bits 10:11 - 11:10\\] Selects IO current mode of this IO."]
2305 #[inline]
2306 pub fn iocurr(&mut self) -> _IOCURRW {
2307 _IOCURRW { w: self }
2308 }
2309 #[doc = "Bits 8:9 - 9:8\\] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR"]
2310 #[inline]
2311 pub fn iostr(&mut self) -> _IOSTRW {
2312 _IOSTRW { w: self }
2313 }
2314 #[doc = "Bit 7 - 7:7\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event"]
2315 #[inline]
2316 pub fn ioev_rtc_en(&mut self) -> _IOEV_RTC_ENW {
2317 _IOEV_RTC_ENW { w: self }
2318 }
2319 #[doc = "Bit 6 - 6:6\\] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event"]
2320 #[inline]
2321 pub fn ioev_mcu_wu_en(&mut self) -> _IOEV_MCU_WU_ENW {
2322 _IOEV_MCU_WU_ENW { w: self }
2323 }
2324 #[doc = "Bits 0:5 - 5:0\\] Selects usage for DIO5"]
2325 #[inline]
2326 pub fn port_id(&mut self) -> _PORT_IDW {
2327 _PORT_IDW { w: self }
2328 }
2329}