cc13x2_cc26x2_pac/i2s0/
aiffmtcfg.rs1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::AIFFMTCFG {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct RESERVED16R {
47 bits: u16,
48}
49impl RESERVED16R {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u16 {
53 self.bits
54 }
55}
56#[doc = r" Value of the field"]
57pub struct DATA_DELAYR {
58 bits: u8,
59}
60impl DATA_DELAYR {
61 #[doc = r" Value of the field as raw bits"]
62 #[inline]
63 pub fn bits(&self) -> u8 {
64 self.bits
65 }
66}
67#[doc = "Possible values of the field `MEM_LEN_24`"]
68#[derive(Clone, Copy, Debug, PartialEq)]
69pub enum MEM_LEN_24R {
70 #[doc = "24-bit (one 8 bit and one 16 bit locked access per sample)"]
71 _24BIT,
72 #[doc = "16-bit (one 16 bit access per sample)"]
73 _16BIT,
74}
75impl MEM_LEN_24R {
76 #[doc = r" Returns `true` if the bit is clear (0)"]
77 #[inline]
78 pub fn bit_is_clear(&self) -> bool {
79 !self.bit()
80 }
81 #[doc = r" Returns `true` if the bit is set (1)"]
82 #[inline]
83 pub fn bit_is_set(&self) -> bool {
84 self.bit()
85 }
86 #[doc = r" Value of the field as raw bits"]
87 #[inline]
88 pub fn bit(&self) -> bool {
89 match *self {
90 MEM_LEN_24R::_24BIT => true,
91 MEM_LEN_24R::_16BIT => false,
92 }
93 }
94 #[allow(missing_docs)]
95 #[doc(hidden)]
96 #[inline]
97 pub fn _from(value: bool) -> MEM_LEN_24R {
98 match value {
99 true => MEM_LEN_24R::_24BIT,
100 false => MEM_LEN_24R::_16BIT,
101 }
102 }
103 #[doc = "Checks if the value of the field is `_24BIT`"]
104 #[inline]
105 pub fn is_24bit(&self) -> bool {
106 *self == MEM_LEN_24R::_24BIT
107 }
108 #[doc = "Checks if the value of the field is `_16BIT`"]
109 #[inline]
110 pub fn is_16bit(&self) -> bool {
111 *self == MEM_LEN_24R::_16BIT
112 }
113}
114#[doc = "Possible values of the field `SMPL_EDGE`"]
115#[derive(Clone, Copy, Debug, PartialEq)]
116pub enum SMPL_EDGER {
117 #[doc = "Data is sampled on the positive edge and clocked out on the negative edge."]
118 POS,
119 #[doc = "Data is sampled on the negative edge and clocked out on the positive edge."]
120 NEG,
121}
122impl SMPL_EDGER {
123 #[doc = r" Returns `true` if the bit is clear (0)"]
124 #[inline]
125 pub fn bit_is_clear(&self) -> bool {
126 !self.bit()
127 }
128 #[doc = r" Returns `true` if the bit is set (1)"]
129 #[inline]
130 pub fn bit_is_set(&self) -> bool {
131 self.bit()
132 }
133 #[doc = r" Value of the field as raw bits"]
134 #[inline]
135 pub fn bit(&self) -> bool {
136 match *self {
137 SMPL_EDGER::POS => true,
138 SMPL_EDGER::NEG => false,
139 }
140 }
141 #[allow(missing_docs)]
142 #[doc(hidden)]
143 #[inline]
144 pub fn _from(value: bool) -> SMPL_EDGER {
145 match value {
146 true => SMPL_EDGER::POS,
147 false => SMPL_EDGER::NEG,
148 }
149 }
150 #[doc = "Checks if the value of the field is `POS`"]
151 #[inline]
152 pub fn is_pos(&self) -> bool {
153 *self == SMPL_EDGER::POS
154 }
155 #[doc = "Checks if the value of the field is `NEG`"]
156 #[inline]
157 pub fn is_neg(&self) -> bool {
158 *self == SMPL_EDGER::NEG
159 }
160}
161#[doc = r" Value of the field"]
162pub struct DUAL_PHASER {
163 bits: bool,
164}
165impl DUAL_PHASER {
166 #[doc = r" Value of the field as raw bits"]
167 #[inline]
168 pub fn bit(&self) -> bool {
169 self.bits
170 }
171 #[doc = r" Returns `true` if the bit is clear (0)"]
172 #[inline]
173 pub fn bit_is_clear(&self) -> bool {
174 !self.bit()
175 }
176 #[doc = r" Returns `true` if the bit is set (1)"]
177 #[inline]
178 pub fn bit_is_set(&self) -> bool {
179 self.bit()
180 }
181}
182#[doc = r" Value of the field"]
183pub struct WORD_LENR {
184 bits: u8,
185}
186impl WORD_LENR {
187 #[doc = r" Value of the field as raw bits"]
188 #[inline]
189 pub fn bits(&self) -> u8 {
190 self.bits
191 }
192}
193#[doc = r" Proxy"]
194pub struct _RESERVED16W<'a> {
195 w: &'a mut W,
196}
197impl<'a> _RESERVED16W<'a> {
198 #[doc = r" Writes raw bits to the field"]
199 #[inline]
200 pub unsafe fn bits(self, value: u16) -> &'a mut W {
201 const MASK: u16 = 65535;
202 const OFFSET: u8 = 16;
203 self.w.bits &= !((MASK as u32) << OFFSET);
204 self.w.bits |= ((value & MASK) as u32) << OFFSET;
205 self.w
206 }
207}
208#[doc = r" Proxy"]
209pub struct _DATA_DELAYW<'a> {
210 w: &'a mut W,
211}
212impl<'a> _DATA_DELAYW<'a> {
213 #[doc = r" Writes raw bits to the field"]
214 #[inline]
215 pub unsafe fn bits(self, value: u8) -> &'a mut W {
216 const MASK: u8 = 255;
217 const OFFSET: u8 = 8;
218 self.w.bits &= !((MASK as u32) << OFFSET);
219 self.w.bits |= ((value & MASK) as u32) << OFFSET;
220 self.w
221 }
222}
223#[doc = "Values that can be written to the field `MEM_LEN_24`"]
224pub enum MEM_LEN_24W {
225 #[doc = "24-bit (one 8 bit and one 16 bit locked access per sample)"]
226 _24BIT,
227 #[doc = "16-bit (one 16 bit access per sample)"]
228 _16BIT,
229}
230impl MEM_LEN_24W {
231 #[allow(missing_docs)]
232 #[doc(hidden)]
233 #[inline]
234 pub fn _bits(&self) -> bool {
235 match *self {
236 MEM_LEN_24W::_24BIT => true,
237 MEM_LEN_24W::_16BIT => false,
238 }
239 }
240}
241#[doc = r" Proxy"]
242pub struct _MEM_LEN_24W<'a> {
243 w: &'a mut W,
244}
245impl<'a> _MEM_LEN_24W<'a> {
246 #[doc = r" Writes `variant` to the field"]
247 #[inline]
248 pub fn variant(self, variant: MEM_LEN_24W) -> &'a mut W {
249 {
250 self.bit(variant._bits())
251 }
252 }
253 #[doc = "24-bit (one 8 bit and one 16 bit locked access per sample)"]
254 #[inline]
255 pub fn _24bit(self) -> &'a mut W {
256 self.variant(MEM_LEN_24W::_24BIT)
257 }
258 #[doc = "16-bit (one 16 bit access per sample)"]
259 #[inline]
260 pub fn _16bit(self) -> &'a mut W {
261 self.variant(MEM_LEN_24W::_16BIT)
262 }
263 #[doc = r" Sets the field bit"]
264 pub fn set_bit(self) -> &'a mut W {
265 self.bit(true)
266 }
267 #[doc = r" Clears the field bit"]
268 pub fn clear_bit(self) -> &'a mut W {
269 self.bit(false)
270 }
271 #[doc = r" Writes raw bits to the field"]
272 #[inline]
273 pub fn bit(self, value: bool) -> &'a mut W {
274 const MASK: bool = true;
275 const OFFSET: u8 = 7;
276 self.w.bits &= !((MASK as u32) << OFFSET);
277 self.w.bits |= ((value & MASK) as u32) << OFFSET;
278 self.w
279 }
280}
281#[doc = "Values that can be written to the field `SMPL_EDGE`"]
282pub enum SMPL_EDGEW {
283 #[doc = "Data is sampled on the positive edge and clocked out on the negative edge."]
284 POS,
285 #[doc = "Data is sampled on the negative edge and clocked out on the positive edge."]
286 NEG,
287}
288impl SMPL_EDGEW {
289 #[allow(missing_docs)]
290 #[doc(hidden)]
291 #[inline]
292 pub fn _bits(&self) -> bool {
293 match *self {
294 SMPL_EDGEW::POS => true,
295 SMPL_EDGEW::NEG => false,
296 }
297 }
298}
299#[doc = r" Proxy"]
300pub struct _SMPL_EDGEW<'a> {
301 w: &'a mut W,
302}
303impl<'a> _SMPL_EDGEW<'a> {
304 #[doc = r" Writes `variant` to the field"]
305 #[inline]
306 pub fn variant(self, variant: SMPL_EDGEW) -> &'a mut W {
307 {
308 self.bit(variant._bits())
309 }
310 }
311 #[doc = "Data is sampled on the positive edge and clocked out on the negative edge."]
312 #[inline]
313 pub fn pos(self) -> &'a mut W {
314 self.variant(SMPL_EDGEW::POS)
315 }
316 #[doc = "Data is sampled on the negative edge and clocked out on the positive edge."]
317 #[inline]
318 pub fn neg(self) -> &'a mut W {
319 self.variant(SMPL_EDGEW::NEG)
320 }
321 #[doc = r" Sets the field bit"]
322 pub fn set_bit(self) -> &'a mut W {
323 self.bit(true)
324 }
325 #[doc = r" Clears the field bit"]
326 pub fn clear_bit(self) -> &'a mut W {
327 self.bit(false)
328 }
329 #[doc = r" Writes raw bits to the field"]
330 #[inline]
331 pub fn bit(self, value: bool) -> &'a mut W {
332 const MASK: bool = true;
333 const OFFSET: u8 = 6;
334 self.w.bits &= !((MASK as u32) << OFFSET);
335 self.w.bits |= ((value & MASK) as u32) << OFFSET;
336 self.w
337 }
338}
339#[doc = r" Proxy"]
340pub struct _DUAL_PHASEW<'a> {
341 w: &'a mut W,
342}
343impl<'a> _DUAL_PHASEW<'a> {
344 #[doc = r" Sets the field bit"]
345 pub fn set_bit(self) -> &'a mut W {
346 self.bit(true)
347 }
348 #[doc = r" Clears the field bit"]
349 pub fn clear_bit(self) -> &'a mut W {
350 self.bit(false)
351 }
352 #[doc = r" Writes raw bits to the field"]
353 #[inline]
354 pub fn bit(self, value: bool) -> &'a mut W {
355 const MASK: bool = true;
356 const OFFSET: u8 = 5;
357 self.w.bits &= !((MASK as u32) << OFFSET);
358 self.w.bits |= ((value & MASK) as u32) << OFFSET;
359 self.w
360 }
361}
362#[doc = r" Proxy"]
363pub struct _WORD_LENW<'a> {
364 w: &'a mut W,
365}
366impl<'a> _WORD_LENW<'a> {
367 #[doc = r" Writes raw bits to the field"]
368 #[inline]
369 pub unsafe fn bits(self, value: u8) -> &'a mut W {
370 const MASK: u8 = 31;
371 const OFFSET: u8 = 0;
372 self.w.bits &= !((MASK as u32) << OFFSET);
373 self.w.bits |= ((value & MASK) as u32) << OFFSET;
374 self.w
375 }
376}
377impl R {
378 #[doc = r" Value of the register as raw bits"]
379 #[inline]
380 pub fn bits(&self) -> u32 {
381 self.bits
382 }
383 #[doc = "Bits 16:31 - 31:16\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
384 #[inline]
385 pub fn reserved16(&self) -> RESERVED16R {
386 let bits = {
387 const MASK: u16 = 65535;
388 const OFFSET: u8 = 16;
389 ((self.bits >> OFFSET) & MASK as u32) as u16
390 };
391 RESERVED16R { bits }
392 }
393 #[doc = "Bits 8:15 - 15:8\\] The number of BCLK periods between a WCLK edge and MSB of the first word in a phase: 0x00: LJF and DSP format 0x01: I2S and DSP format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired."]
394 #[inline]
395 pub fn data_delay(&self) -> DATA_DELAYR {
396 let bits = {
397 const MASK: u8 = 255;
398 const OFFSET: u8 = 8;
399 ((self.bits >> OFFSET) & MASK as u32) as u8
400 };
401 DATA_DELAYR { bits }
402 }
403 #[doc = "Bit 7 - 7:7\\] The size of each word stored to or loaded from memory:"]
404 #[inline]
405 pub fn mem_len_24(&self) -> MEM_LEN_24R {
406 MEM_LEN_24R::_from({
407 const MASK: bool = true;
408 const OFFSET: u8 = 7;
409 ((self.bits >> OFFSET) & MASK as u32) != 0
410 })
411 }
412 #[doc = "Bit 6 - 6:6\\] On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK."]
413 #[inline]
414 pub fn smpl_edge(&self) -> SMPL_EDGER {
415 SMPL_EDGER::_from({
416 const MASK: bool = true;
417 const OFFSET: u8 = 6;
418 ((self.bits >> OFFSET) & MASK as u32) != 0
419 })
420 }
421 #[doc = "Bit 5 - 5:5\\] Selects dual- or single-phase format. 0: Single-phase: DSP format 1: Dual-phase: I2S, LJF and RJF formats"]
422 #[inline]
423 pub fn dual_phase(&self) -> DUAL_PHASER {
424 let bits = {
425 const MASK: bool = true;
426 const OFFSET: u8 = 5;
427 ((self.bits >> OFFSET) & MASK as u32) != 0
428 };
429 DUAL_PHASER { bits }
430 }
431 #[doc = "Bits 0:4 - 4:0\\] Number of bits per word (8-24): In single-phase format, this is the exact number of bits per word. In dual-phase format, this is the maximum number of bits per word. Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from this alignment will either be truncated or zero padded."]
432 #[inline]
433 pub fn word_len(&self) -> WORD_LENR {
434 let bits = {
435 const MASK: u8 = 31;
436 const OFFSET: u8 = 0;
437 ((self.bits >> OFFSET) & MASK as u32) as u8
438 };
439 WORD_LENR { bits }
440 }
441}
442impl W {
443 #[doc = r" Reset value of the register"]
444 #[inline]
445 pub fn reset_value() -> W {
446 W { bits: 368 }
447 }
448 #[doc = r" Writes raw bits to the register"]
449 #[inline]
450 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
451 self.bits = bits;
452 self
453 }
454 #[doc = "Bits 16:31 - 31:16\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
455 #[inline]
456 pub fn reserved16(&mut self) -> _RESERVED16W {
457 _RESERVED16W { w: self }
458 }
459 #[doc = "Bits 8:15 - 15:8\\] The number of BCLK periods between a WCLK edge and MSB of the first word in a phase: 0x00: LJF and DSP format 0x01: I2S and DSP format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired."]
460 #[inline]
461 pub fn data_delay(&mut self) -> _DATA_DELAYW {
462 _DATA_DELAYW { w: self }
463 }
464 #[doc = "Bit 7 - 7:7\\] The size of each word stored to or loaded from memory:"]
465 #[inline]
466 pub fn mem_len_24(&mut self) -> _MEM_LEN_24W {
467 _MEM_LEN_24W { w: self }
468 }
469 #[doc = "Bit 6 - 6:6\\] On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK."]
470 #[inline]
471 pub fn smpl_edge(&mut self) -> _SMPL_EDGEW {
472 _SMPL_EDGEW { w: self }
473 }
474 #[doc = "Bit 5 - 5:5\\] Selects dual- or single-phase format. 0: Single-phase: DSP format 1: Dual-phase: I2S, LJF and RJF formats"]
475 #[inline]
476 pub fn dual_phase(&mut self) -> _DUAL_PHASEW {
477 _DUAL_PHASEW { w: self }
478 }
479 #[doc = "Bits 0:4 - 4:0\\] Number of bits per word (8-24): In single-phase format, this is the exact number of bits per word. In dual-phase format, this is the maximum number of bits per word. Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from this alignment will either be truncated or zero padded."]
480 #[inline]
481 pub fn word_len(&mut self) -> _WORD_LENW {
482 _WORD_LENW { w: self }
483 }
484}