[−][src]Struct cc13x2_cc26x2_pac::prcm::i2sbclkdiv::W
Value to write to the register
Methods
impl W
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pub fn reset_value() -> W
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Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self
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Writes raw bits to the register
pub fn reserved10(&mut self) -> _RESERVED10W
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Bits 10:31 - 31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn bdiv(&mut self) -> _BDIVW
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Bits 0:9 - 9:0] An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: BCLK = MCUCLK/BDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written
Auto Trait Implementations
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