Struct cc13x2_cc26x2_pac::i2s0::aiffmtcfg::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved16(&mut self) -> _RESERVED16W

Bits 16:31 - 31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn data_delay(&mut self) -> _DATA_DELAYW

Bits 8:15 - 15:8] The number of BCLK periods between a WCLK edge and MSB of the first word in a phase: 0x00: LJF and DSP format 0x01: I2S and DSP format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.

pub fn mem_len_24(&mut self) -> _MEM_LEN_24W

Bit 7 - 7:7] The size of each word stored to or loaded from memory:

pub fn smpl_edge(&mut self) -> _SMPL_EDGEW

Bit 6 - 6:6] On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.

pub fn dual_phase(&mut self) -> _DUAL_PHASEW

Bit 5 - 5:5] Selects dual- or single-phase format. 0: Single-phase: DSP format 1: Dual-phase: I2S, LJF and RJF formats

pub fn word_len(&mut self) -> _WORD_LENW

Bits 0:4 - 4:0] Number of bits per word (8-24): In single-phase format, this is the exact number of bits per word. In dual-phase format, this is the maximum number of bits per word. Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from this alignment will either be truncated or zero padded.