Struct cc13x2_cc26x2_hal::udma0::status::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn test(&self) -> TESTR

Bits 28:31 - 31:28] 0x0: Controller does not include the integration test logic 0x1: Controller includes the integration test logic 0x2: Undefined ... 0xF: Undefined

pub fn reserved21(&self) -> RESERVED21R

Bits 21:27 - 27:21] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn totalchannels(&self) -> TOTALCHANNELSR

Bits 16:20 - 20:16] Register value returns number of available uDMA channels minus one. For example a read out value of: 0x00: Show that the controller is configured to use 1 uDMA channel 0x01: Shows that the controller is configured to use 2 uDMA channels ... 0x1F: Shows that the controller is configured to use 32 uDMA channels (32-1=31=0x1F)

pub fn reserved8(&self) -> RESERVED8R

Bits 8:15 - 15:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn state(&self) -> STATER

Bits 4:7 - 7:4] Current state of the control state machine. State can be one of the following: 0x0: Idle 0x1: Reading channel controller data 0x2: Reading source data end pointer 0x3: Reading destination data end pointer 0x4: Reading source data 0x5: Writing destination data 0x6: Waiting for uDMA request to clear 0x7: Writing channel controller data 0x8: Stalled 0x9: Done 0xA: Peripheral scatter-gather transition 0xB: Undefined ... 0xF: Undefined.

pub fn reserved1(&self) -> RESERVED1R

Bits 1:3 - 3:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn masterenable(&self) -> MASTERENABLER

Bit 0 - 0:0] Shows the enable status of the controller as configured by CFG.MASTERENABLE: 0: Controller is disabled 1: Controller is enabled