[][src]Struct cc13x2_cc26x2_hal::uart0::icr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R[src]

pub fn bits(&self) -> u32[src]

Value of the register as raw bits

pub fn reserved12(&self) -> RESERVED12R[src]

Bits 12:31 - 31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn eotic(&self) -> EOTICR[src]

Bit 11 - 11:11] End of Transmission interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). Writing 0 has no effect.

pub fn oeic(&self) -> OEICR[src]

Bit 10 - 10:10] Overrun error interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). Writing 0 has no effect.

pub fn beic(&self) -> BEICR[src]

Bit 9 - 9:9] Break error interrupt clear: Writing 1 to this field clears the break error interrupt (RIS.BERIS). Writing 0 has no effect.

pub fn peic(&self) -> PEICR[src]

Bit 8 - 8:8] Parity error interrupt clear: Writing 1 to this field clears the parity error interrupt (RIS.PERIS). Writing 0 has no effect.

pub fn feic(&self) -> FEICR[src]

Bit 7 - 7:7] Framing error interrupt clear: Writing 1 to this field clears the framing error interrupt (RIS.FERIS). Writing 0 has no effect.

pub fn rtic(&self) -> RTICR[src]

Bit 6 - 6:6] Receive timeout interrupt clear: Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). Writing 0 has no effect.

pub fn txic(&self) -> TXICR[src]

Bit 5 - 5:5] Transmit interrupt clear: Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 has no effect.

pub fn rxic(&self) -> RXICR[src]

Bit 4 - 4:4] Receive interrupt clear: Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 has no effect.

pub fn reserved2(&self) -> RESERVED2R[src]

Bits 2:3 - 3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0

pub fn ctsmic(&self) -> CTSMICR[src]

Bit 1 - 1:1] Clear to Send (CTS) modem interrupt clear: Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). Writing 0 has no effect.

pub fn reserved0(&self) -> RESERVED0R[src]

Bit 0 - 0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0.

Auto Trait Implementations

impl Send for R

impl Sync for R

Blanket Implementations

impl<T> From for T[src]

impl<T, U> TryFrom for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T, U> Into for T where
    U: From<T>, 
[src]

impl<T> Borrow for T where
    T: ?Sized
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impl<T> BorrowMut for T where
    T: ?Sized
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impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Same for T

type Output = T

Should always be Self