[][src]Struct cc13x2_cc26x2_hal::trng::ctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R[src]

pub fn bits(&self) -> u32[src]

Value of the register as raw bits

pub fn startup_cycles(&self) -> STARTUP_CYCLESR[src]

Bits 16:31 - 31:16] This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup. If the written value of this field is zero, the number of samples is 2^24, otherwise the number of samples equals the written value times 2^8. 0x0000: 2^24 samples 0x0001: 12^8 samples 0x0002: 22^8 samples 0x0003: 32^8 samples ... 0x8000: 327682^8 samples 0xC000: 491522^8 samples ... 0xFFFF: 655352^8 samples This field can only be modified while TRNG_EN is 0. If 1 an update will be ignored.

pub fn reserved11(&self) -> RESERVED11R[src]

Bits 11:15 - 15:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn trng_en(&self) -> TRNG_ENR[src]

Bit 10 - 10:10] 0: Forces all TRNG logic back into the idle state immediately. 1: Starts TRNG, gathering entropy from the FROs for the number of samples determined by STARTUP_CYCLES.

pub fn reserved3(&self) -> RESERVED3R[src]

Bits 3:9 - 9:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn no_lfsr_fb(&self) -> NO_LFSR_FBR[src]

Bit 2 - 2:2] 1: Remove XNOR feedback from the main LFSR, converting it into a normal shift register for the XOR-ed outputs of the FROs (shifting data in on the LSB side). A '1' also forces the LFSR to sample continuously. This bit can only be set to '1' when TEST_MODE is also set to '1' and should not be used for other than test purposes

pub fn test_mode(&self) -> TEST_MODER[src]

Bit 1 - 1:1] 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter are automatically cleared before enabling access) and keeps IRQFLAGSTAT.NEED_CLOCK at '1'. This bit shall not be used unless you need to change the LFSR seed prior to creating a new random value. All other testing is done external to register control.

pub fn reserved0(&self) -> RESERVED0R[src]

Bit 0 - 0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

Auto Trait Implementations

impl Send for R

impl Sync for R

Blanket Implementations

impl<T> From for T[src]

impl<T, U> TryFrom for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T, U> Into for T where
    U: From<T>, 
[src]

impl<T> Borrow for T where
    T: ?Sized
[src]

impl<T> BorrowMut for T where
    T: ?Sized
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impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Same for T

type Output = T

Should always be Self