Struct cc13x2_cc26x2_hal::ssi1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cr0: CR0,
    pub cr1: CR1,
    pub dr: DR,
    pub sr: SR,
    pub cpsr: CPSR,
    pub imsc: IMSC,
    pub ris: RIS,
    pub mis: MIS,
    pub icr: ICR,
    pub dmacr: DMACR,
    pub reserved1: RESERVED1,
    pub reserved2: RESERVED2,
    // some fields omitted
}

Register block

Fields

cr0: CR0

0x00 - Control 0

cr1: CR1

0x04 - Control 1

dr: DR

0x08 - Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.

sr: SR

0x0c - Status

cpsr: CPSR

0x10 - Clock Prescale

imsc: IMSC

0x14 - Interrupt Mask Set and Clear

ris: RIS

0x18 - Raw Interrupt Status

mis: MIS

0x1c - Masked Interrupt Status

icr: ICR

0x20 - Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

dmacr: DMACR

0x24 - DMA Control

reserved1: RESERVED1

0x28 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

reserved2: RESERVED2

0x90 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.