Struct cc13x2_cc26x2_hal::sram_mmr::mem_ctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved24(&self) -> RESERVED24R

Bits 2:31 - 31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn mem_busy(&self) -> MEM_BUSYR

Bit 1 - 1:1] Memory Busy status 0: Memory accepts transfers 1: Memory controller is busy during initialization. Read and write transfers are not performed.

pub fn mem_clr_en(&self) -> MEM_CLR_ENR

Bit 0 - 0:0] Memory Contents Initialization enable Writing 1 to MEM_CLR_EN will start memory initialization. The contents of all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until memory initialization has completed.