Struct cc13x2_cc26x2_hal::rfc_pwr::pwmclken::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved11(&mut self) -> _RESERVED11W

Bits 11:31 - 31:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn rfctrc(&mut self) -> _RFCTRCW

Bit 10 - 10:10] Enable clock to the RF Core Tracer (RFCTRC) module.

pub fn fsca(&mut self) -> _FSCAW

Bit 9 - 9:9] Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module.

pub fn pha(&mut self) -> _PHAW

Bit 8 - 8:8] Enable clock to the Packet Handling Accelerator (PHA) module.

pub fn rat(&mut self) -> _RATW

Bit 7 - 7:7] Enable clock to the Radio Timer (RAT) module.

pub fn rferam(&mut self) -> _RFERAMW

Bit 6 - 6:6] Enable clock to the RF Engine RAM module.

pub fn rfe(&mut self) -> _RFEW

Bit 5 - 5:5] Enable clock to the RF Engine (RFE) module.

pub fn mdmram(&mut self) -> _MDMRAMW

Bit 4 - 4:4] Enable clock to the Modem RAM module.

pub fn mdm(&mut self) -> _MDMW

Bit 3 - 3:3] Enable clock to the Modem (MDM) module.

pub fn cperam(&mut self) -> _CPERAMW

Bit 2 - 2:2] Enable clock to the Command and Packet Engine (CPE) RAM module. As part of RF Core initialization, set this bit together with CPE bit to enable CPE to boot.

pub fn cpe(&mut self) -> _CPEW

Bit 1 - 1:1] Enable processor clock (hclk) to the Command and Packet Engine (CPE). As part of RF Core initialization, set this bit together with CPERAM bit to enable CPE to boot.

pub fn rfc(&mut self) -> _RFCW

Bit 0 - 0:0] Enable essential clocks for the RF Core interface. This includes the interconnect, the radio doorbell DBELL command interface, the power management (PWR) clock control module, and bus clock (sclk) for the CPE. To remove possibility of locking yourself out from the RF Core, this bit can not be cleared. If you need to disable all clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register.