Struct cc13x2_cc26x2_hal::pka::function::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved25(&self) -> RESERVED25R

Bits 25:31 - 31:25] Set to zero on write, ignore on read

pub fn stall_result(&self) -> STALL_RESULTR

Bit 24 - 24:24] When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW registers, as well as resetting the run bit is stalled beyond the point that a running operation is actually finished. Use this to allow software enough time to read results from a previous operation when the newly started operation is known to take only a short amount of time. If a result is waiting, the result registers is updated and the run bit is reset in the clock cycle following writing the stall result bit back to 0b. The Stall result function may only be used for basic PKCP operations.

pub fn reserved16(&self) -> RESERVED16R

Bits 16:23 - 23:16] Set to zero on write, ignore on read

pub fn run(&self) -> RUNR

Bit 15 - 15:15] The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation. This bit is reset low automatically when the operation is complete. After a reset, the run bit is always set to 1b. Depending on the option, program ROM or program RAM, the following applies: Program ROM - The first sequencer instruction sets the bit to 0b. This is done immediately after the hardware reset is released. Program RAM - The sequencer must set the bit to 0b. As a valid firmware may not have been loaded, the sequencer is held in software reset after the hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the FW image is loaded and the Reset bit is cleared, the sequencer starts to execute the FW. The first instruction clears the run bit. In both cases a few clock cycles are needed before the first instruction is executed and the run bit state has been propagated.

pub fn sequencer_operations(&self) -> SEQUENCER_OPERATIONSR

Bits 12:14 - 14:12] These bits select the complex sequencer operation to perform: 0x0: None 0x1: ExpMod-CRT 0x2: ECmontMUL 0x3: ECC-ADD (if available in firmware, otherwise reserved) 0x4: ExpMod-ACT2 0x5: ECC-MUL (if available in firmware, otherwise reserved) 0x6: ExpMod-variable 0x7: ModInv (if available in firmware, otherwise reserved) The encoding of these operations is determined by sequencer firmware.

pub fn copy(&self) -> COPYR

Bit 11 - 11:11] Perform copy operation

pub fn compare(&self) -> COMPARER

Bit 10 - 10:10] Perform compare operation

pub fn modulo(&self) -> MODULOR

Bit 9 - 9:9] Perform modulo operation

pub fn divide(&self) -> DIVIDER

Bit 8 - 8:8] Perform divide operation

pub fn lshift(&self) -> LSHIFTR

Bit 7 - 7:7] Perform left shift operation

pub fn rshift(&self) -> RSHIFTR

Bit 6 - 6:6] Perform right shift operation

pub fn subtract(&self) -> SUBTRACTR

Bit 5 - 5:5] Perform subtract operation

pub fn add(&self) -> ADDR

Bit 4 - 4:4] Perform add operation

pub fn ms_one(&self) -> MS_ONER

Bit 3 - 3:3] Loads the location of the Most Significant one bit within the result word indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS register - can only be used with basic PKCP operations, except for Divide, Modulo and Compare.

pub fn reserved2(&self) -> RESERVED2R

Bit 2 - 2:2] Set to zero on write, ignore on read

pub fn addsub(&self) -> ADDSUBR

Bit 1 - 1:1] Perform combined add/subtract operation

pub fn multiply(&self) -> MULTIPLYR

Bit 0 - 0:0] Perform multiply operation