Struct cc13x2_cc26x2_hal::i2s0::irqflags::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved6(&mut self) -> _RESERVED6W

Bits 6:31 - 31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn aif_dma_in(&mut self) -> _AIF_DMA_INW

Bit 5 - 5:5] Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register for details.

pub fn aif_dma_out(&mut self) -> _AIF_DMA_OUTW

Bit 4 - 4:4] Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT register for details

pub fn wclk_timeout(&mut self) -> _WCLK_TIMEOUTW

Bit 3 - 3:3] Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_TIMEOUT).

pub fn bus_err(&mut self) -> _BUS_ERRW

Bit 2 - 2:2] Set when a DMA operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow). This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.BUS_ERR). Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined.

pub fn wclk_err(&mut self) -> _WCLK_ERRW

Bit 1 - 1:1] Set when: - An unexpected WCLK edge occurs during the data delay period of a phase. Note unexpected WCLK edges during the word and idle periods of the phase are not detected. - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles apart. - In single-phase mode, when a WCLK pulse occurs before the last channel. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_ERR).

pub fn ptr_err(&mut self) -> _PTR_ERRW

Bit 0 - 0:0] Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.PTR_ERR).