Struct cc13x2_cc26x2_hal::i2c0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub soar: SOAR,
    pub sstat: SSTAT,
    pub sdr: SDR,
    pub simr: SIMR,
    pub sris: SRIS,
    pub smis: SMIS,
    pub sicr: SICR,
    pub msa: MSA,
    pub mstat: MSTAT,
    pub mdr: MDR,
    pub mtpr: MTPR,
    pub mimr: MIMR,
    pub mris: MRIS,
    pub mmis: MMIS,
    pub micr: MICR,
    pub mcr: MCR,
    // some fields omitted
}

Register block

Fields

soar: SOAR

0x00 - Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus.

sstat: SSTAT

0x04 - Slave Status Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read.

sdr: SDR

0x08 - Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state.

simr: SIMR

0x0c - Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.

sris: SRIS

0x10 - Slave Raw Interrupt Status This register shows the unmasked interrupt status.

smis: SMIS

0x14 - Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR).

sicr: SICR

0x18 - Slave Interrupt Clear This register clears the raw interrupt SRIS.

msa: MSA

0x800 - Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit.

mstat: MSTAT

0x804 - Master Status

mdr: MDR

0x808 - Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state.

mtpr: MTPR

0x80c - I2C Master Timer Period This register specifies the period of the SCL clock.

mimr: MIMR

0x810 - Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.

mris: MRIS

0x814 - Master Raw Interrupt Status This register show the unmasked interrupt status.

mmis: MMIS

0x818 - Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR).

micr: MICR

0x81c - Master Interrupt Clear This register clears the raw and masked interrupt.

mcr: MCR

0x820 - Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback.