Struct cc13x2_cc26x2_hal::cpu_scs::DEMCR

pub struct DEMCR { /* fields omitted */ }

Debug Exception and Monitor Control The purpose of this register is vector catching and debug monitor control. This register manages exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception support. This register is not reset on a system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset handler or later, or by the AHB-AP port. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.

Methods

impl DEMCR

pub fn modify<F>(&self, f: F) where
    F: FnOnce(&R, &'w mut W) -> &'w mut W, 

Modifies the contents of the register

pub fn read(&self) -> R

Reads the contents of the register

pub fn write<F>(&self, f: F) where
    F: FnOnce(&mut W) -> &mut W, 

Writes to the register

pub fn reset(&self)

Writes the reset value to the register