Struct cc13x2_cc26x2_hal::cpu_scs::nvic_iabr0::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn active31(&self) -> ACTIVE31R

Bit 31 - 31:31] Reading 0 from this bit implies that interrupt line 31 is not active. Reading 1 from this bit implies that the interrupt line 31 is active (See EVENT:CPUIRQSEL31.EV for details).

pub fn active30(&self) -> ACTIVE30R

Bit 30 - 30:30] Reading 0 from this bit implies that interrupt line 30 is not active. Reading 1 from this bit implies that the interrupt line 30 is active (See EVENT:CPUIRQSEL30.EV for details).

pub fn active29(&self) -> ACTIVE29R

Bit 29 - 29:29] Reading 0 from this bit implies that interrupt line 29 is not active. Reading 1 from this bit implies that the interrupt line 29 is active (See EVENT:CPUIRQSEL29.EV for details).

pub fn active28(&self) -> ACTIVE28R

Bit 28 - 28:28] Reading 0 from this bit implies that interrupt line 28 is not active. Reading 1 from this bit implies that the interrupt line 28 is active (See EVENT:CPUIRQSEL28.EV for details).

pub fn active27(&self) -> ACTIVE27R

Bit 27 - 27:27] Reading 0 from this bit implies that interrupt line 27 is not active. Reading 1 from this bit implies that the interrupt line 27 is active (See EVENT:CPUIRQSEL27.EV for details).

pub fn active26(&self) -> ACTIVE26R

Bit 26 - 26:26] Reading 0 from this bit implies that interrupt line 26 is not active. Reading 1 from this bit implies that the interrupt line 26 is active (See EVENT:CPUIRQSEL26.EV for details).

pub fn active25(&self) -> ACTIVE25R

Bit 25 - 25:25] Reading 0 from this bit implies that interrupt line 25 is not active. Reading 1 from this bit implies that the interrupt line 25 is active (See EVENT:CPUIRQSEL25.EV for details).

pub fn active24(&self) -> ACTIVE24R

Bit 24 - 24:24] Reading 0 from this bit implies that interrupt line 24 is not active. Reading 1 from this bit implies that the interrupt line 24 is active (See EVENT:CPUIRQSEL24.EV for details).

pub fn active23(&self) -> ACTIVE23R

Bit 23 - 23:23] Reading 0 from this bit implies that interrupt line 23 is not active. Reading 1 from this bit implies that the interrupt line 23 is active (See EVENT:CPUIRQSEL23.EV for details).

pub fn active22(&self) -> ACTIVE22R

Bit 22 - 22:22] Reading 0 from this bit implies that interrupt line 22 is not active. Reading 1 from this bit implies that the interrupt line 22 is active (See EVENT:CPUIRQSEL22.EV for details).

pub fn active21(&self) -> ACTIVE21R

Bit 21 - 21:21] Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details).

pub fn active20(&self) -> ACTIVE20R

Bit 20 - 20:20] Reading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details).

pub fn active19(&self) -> ACTIVE19R

Bit 19 - 19:19] Reading 0 from this bit implies that interrupt line 19 is not active. Reading 1 from this bit implies that the interrupt line 19 is active (See EVENT:CPUIRQSEL19.EV for details).

pub fn active18(&self) -> ACTIVE18R

Bit 18 - 18:18] Reading 0 from this bit implies that interrupt line 18 is not active. Reading 1 from this bit implies that the interrupt line 18 is active (See EVENT:CPUIRQSEL18.EV for details).

pub fn active17(&self) -> ACTIVE17R

Bit 17 - 17:17] Reading 0 from this bit implies that interrupt line 17 is not active. Reading 1 from this bit implies that the interrupt line 17 is active (See EVENT:CPUIRQSEL17.EV for details).

pub fn active16(&self) -> ACTIVE16R

Bit 16 - 16:16] Reading 0 from this bit implies that interrupt line 16 is not active. Reading 1 from this bit implies that the interrupt line 16 is active (See EVENT:CPUIRQSEL16.EV for details).

pub fn active15(&self) -> ACTIVE15R

Bit 15 - 15:15] Reading 0 from this bit implies that interrupt line 15 is not active. Reading 1 from this bit implies that the interrupt line 15 is active (See EVENT:CPUIRQSEL15.EV for details).

pub fn active14(&self) -> ACTIVE14R

Bit 14 - 14:14] Reading 0 from this bit implies that interrupt line 14 is not active. Reading 1 from this bit implies that the interrupt line 14 is active (See EVENT:CPUIRQSEL14.EV for details).

pub fn active13(&self) -> ACTIVE13R

Bit 13 - 13:13] Reading 0 from this bit implies that interrupt line 13 is not active. Reading 1 from this bit implies that the interrupt line 13 is active (See EVENT:CPUIRQSEL13.EV for details).

pub fn active12(&self) -> ACTIVE12R

Bit 12 - 12:12] Reading 0 from this bit implies that interrupt line 12 is not active. Reading 1 from this bit implies that the interrupt line 12 is active (See EVENT:CPUIRQSEL12.EV for details).

pub fn active11(&self) -> ACTIVE11R

Bit 11 - 11:11] Reading 0 from this bit implies that interrupt line 11 is not active. Reading 1 from this bit implies that the interrupt line 11 is active (See EVENT:CPUIRQSEL11.EV for details).

pub fn active10(&self) -> ACTIVE10R

Bit 10 - 10:10] Reading 0 from this bit implies that interrupt line 10 is not active. Reading 1 from this bit implies that the interrupt line 10 is active (See EVENT:CPUIRQSEL10.EV for details).

pub fn active9(&self) -> ACTIVE9R

Bit 9 - 9:9] Reading 0 from this bit implies that interrupt line 9 is not active. Reading 1 from this bit implies that the interrupt line 9 is active (See EVENT:CPUIRQSEL9.EV for details).

pub fn active8(&self) -> ACTIVE8R

Bit 8 - 8:8] Reading 0 from this bit implies that interrupt line 8 is not active. Reading 1 from this bit implies that the interrupt line 8 is active (See EVENT:CPUIRQSEL8.EV for details).

pub fn active7(&self) -> ACTIVE7R

Bit 7 - 7:7] Reading 0 from this bit implies that interrupt line 7 is not active. Reading 1 from this bit implies that the interrupt line 7 is active (See EVENT:CPUIRQSEL7.EV for details).

pub fn active6(&self) -> ACTIVE6R

Bit 6 - 6:6] Reading 0 from this bit implies that interrupt line 6 is not active. Reading 1 from this bit implies that the interrupt line 6 is active (See EVENT:CPUIRQSEL6.EV for details).

pub fn active5(&self) -> ACTIVE5R

Bit 5 - 5:5] Reading 0 from this bit implies that interrupt line 5 is not active. Reading 1 from this bit implies that the interrupt line 5 is active (See EVENT:CPUIRQSEL5.EV for details).

pub fn active4(&self) -> ACTIVE4R

Bit 4 - 4:4] Reading 0 from this bit implies that interrupt line 4 is not active. Reading 1 from this bit implies that the interrupt line 4 is active (See EVENT:CPUIRQSEL4.EV for details).

pub fn active3(&self) -> ACTIVE3R

Bit 3 - 3:3] Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details).

pub fn active2(&self) -> ACTIVE2R

Bit 2 - 2:2] Reading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details).

pub fn active1(&self) -> ACTIVE1R

Bit 1 - 1:1] Reading 0 from this bit implies that interrupt line 1 is not active. Reading 1 from this bit implies that the interrupt line 1 is active (See EVENT:CPUIRQSEL1.EV for details).

pub fn active0(&self) -> ACTIVE0R

Bit 0 - 0:0] Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details).