[][src]Struct cc13x2_cc26x2_hal::cpu_scs::aircr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W[src]

pub fn reset_value() -> W[src]

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self[src]

Writes raw bits to the register

pub fn vectkey(&mut self) -> _VECTKEYW[src]

Bits 16:31 - 31:16] Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05.

pub fn endianess(&mut self) -> _ENDIANESSW[src]

Bit 15 - 15:15] Data endianness bit

pub fn reserved11(&mut self) -> _RESERVED11W[src]

Bits 11:14 - 14:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn prigroup(&mut self) -> _PRIGROUPW[src]

Bits 8:10 - 10:8] Interrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices.

pub fn reserved3(&mut self) -> _RESERVED3W[src]

Bits 3:7 - 7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn sysresetreq(&mut self) -> _SYSRESETREQW[src]

Bit 2 - 2:2] Requests a warm reset. Setting this bit does not prevent Halting Debug from running.

pub fn vectclractive(&mut self) -> _VECTCLRACTIVEW[src]

Bit 1 - 1:1] Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.

pub fn vectreset(&mut self) -> _VECTRESETW[src]

Bit 0 - 0:0] System Reset bit. Resets the system, with the exception of debug components. This bit is reserved for debug use and can be written to 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior.

Auto Trait Implementations

impl Send for W

impl Sync for W

Blanket Implementations

impl<T> From for T[src]

impl<T, U> TryFrom for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T, U> Into for T where
    U: From<T>, 
[src]

impl<T> Borrow for T where
    T: ?Sized
[src]

impl<T> BorrowMut for T where
    T: ?Sized
[src]

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Same for T

type Output = T

Should always be Self