Struct cc13x2_cc26x2_hal::aux_timer2::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ctl: CTL,
    pub target: TARGET,
    pub shdwtarget: SHDWTARGET,
    pub cntr: CNTR,
    pub precfg: PRECFG,
    pub evctl: EVCTL,
    pub pulsetrig: PULSETRIG,
    pub ch0evcfg: CH0EVCFG,
    pub ch0ccfg: CH0CCFG,
    pub ch0pcc: CH0PCC,
    pub ch0cc: CH0CC,
    pub ch1evcfg: CH1EVCFG,
    pub ch1ccfg: CH1CCFG,
    pub ch1pcc: CH1PCC,
    pub ch1cc: CH1CC,
    pub ch2evcfg: CH2EVCFG,
    pub ch2ccfg: CH2CCFG,
    pub ch2pcc: CH2PCC,
    pub ch2cc: CH2CC,
    pub ch3evcfg: CH3EVCFG,
    pub ch3ccfg: CH3CCFG,
    pub ch3pcc: CH3PCC,
    pub ch3cc: CH3CC,
    // some fields omitted
}

Register block

Fields

ctl: CTL

0x00 - Timer Control

target: TARGET

0x04 - Target User defined counter target.

shdwtarget: SHDWTARGET

0x08 - Shadow Target

cntr: CNTR

0x0c - Counter

precfg: PRECFG

0x10 - Clock Prescaler Configuration

evctl: EVCTL

0x14 - Event Control Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected. An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time. The four events connect to the asynchronous AUX event bus: - Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. - Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. - Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. - Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

pulsetrig: PULSETRIG

0x18 - Pulse Trigger

ch0evcfg: CH0EVCFG

0x80 - Channel 0 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

ch0ccfg: CH0CCFG

0x84 - Channel 0 Capture Configuration

ch0pcc: CH0PCC

0x88 - Channel 0 Pipeline Capture Compare

ch0cc: CH0CC

0x8c - Channel 0 Capture Compare

ch1evcfg: CH1EVCFG

0x90 - Channel 1 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

ch1ccfg: CH1CCFG

0x94 - Channel 1 Capture Configuration

ch1pcc: CH1PCC

0x98 - Channel 1 Pipeline Capture Compare

ch1cc: CH1CC

0x9c - Channel 1 Capture Compare

ch2evcfg: CH2EVCFG

0xa0 - Channel 2 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

ch2ccfg: CH2CCFG

0xa4 - Channel 2 Capture Configuration

ch2pcc: CH2PCC

0xa8 - Channel 2 Pipeline Capture Compare

ch2cc: CH2CC

0xac - Channel 2 Capture Compare

ch3evcfg: CH3EVCFG

0xb0 - Channel 3 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

ch3ccfg: CH3CCFG

0xb4 - Channel 3 Capture Configuration

ch3pcc: CH3PCC

0xb8 - Channel 3 Pipeline Capture Compare

ch3cc: CH3CC

0xbc - Channel 3 Capture Compare