Struct cc13x2_cc26x2_hal::aux_evctl::evstat3::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved16(&mut self) -> _RESERVED16W

Bits 16:31 - 31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn aux_timer2_clkswitch_rdy(&mut self) -> _AUX_TIMER2_CLKSWITCH_RDYW

Bit 15 - 15:15] AUX_SYSIF:TIMER2CLKSWITCH.RDY

pub fn aux_dac_hold_active(&mut self) -> _AUX_DAC_HOLD_ACTIVEW

Bit 14 - 14:14] AUX_ANAIF:DACSTAT.HOLD_ACTIVE

pub fn aux_smph_autotake_done(&mut self) -> _AUX_SMPH_AUTOTAKE_DONEW

Bit 13 - 13:13] See AUX_SMPH:AUTOTAKE.SMPH_ID for description.

pub fn aux_adc_fifo_not_empty(&mut self) -> _AUX_ADC_FIFO_NOT_EMPTYW

Bit 12 - 12:12] AUX_ANAIF:ADCFIFOSTAT.EMPTY negated

pub fn aux_adc_fifo_almost_full(&mut self) -> _AUX_ADC_FIFO_ALMOST_FULLW

Bit 11 - 11:11] AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL

pub fn aux_adc_irq(&mut self) -> _AUX_ADC_IRQW

Bit 10 - 10:10] The logical function for this event is configurable. When DMACTL.EN = 1 : Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW When DMACTL.EN = 0 : Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW Bit 7 in UDMA0:DONEMASK must be 0.

pub fn aux_adc_done(&mut self) -> _AUX_ADC_DONEW

Bit 9 - 9:9] AUX_ANAIF ADC conversion done event. Event is synchronized at AUX bus rate.

pub fn aux_isrc_reset_n(&mut self) -> _AUX_ISRC_RESET_NW

Bit 8 - 8:8] AUX_ANAIF:ISRCCTL.RESET_N

pub fn aux_tdc_done(&mut self) -> _AUX_TDC_DONEW

Bit 7 - 7:7] AUX_TDC:STAT.DONE

pub fn aux_timer0_ev(&mut self) -> _AUX_TIMER0_EVW

Bit 6 - 6:6] AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description.

pub fn aux_timer1_ev(&mut self) -> _AUX_TIMER1_EVW

Bit 5 - 5:5] AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description.

pub fn aux_timer2_pulse(&mut self) -> _AUX_TIMER2_PULSEW

Bit 4 - 4:4] AUX_TIMER2 pulse event. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.

pub fn aux_timer2_ev3(&mut self) -> _AUX_TIMER2_EV3W

Bit 3 - 3:3] AUX_TIMER2 event output 3. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.

pub fn aux_timer2_ev2(&mut self) -> _AUX_TIMER2_EV2W

Bit 2 - 2:2] AUX_TIMER2 event output 2. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.

pub fn aux_timer2_ev1(&mut self) -> _AUX_TIMER2_EV1W

Bit 1 - 1:1] AUX_TIMER2 event output 1. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.

pub fn aux_timer2_ev0(&mut self) -> _AUX_TIMER2_EV0W

Bit 0 - 0:0] AUX_TIMER2 event output 0. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.