Struct cc13x2_cc26x2_hal::aon_rtc::ctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved19(&self) -> RESERVED19R

Bits 19:31 - 31:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn comb_ev_mask(&self) -> COMB_EV_MASKR

Bits 16:18 - 18:16] Eventmask selecting which delayed events that form the combined event.

pub fn reserved12(&self) -> RESERVED12R

Bits 12:15 - 15:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn ev_delay(&self) -> EV_DELAYR

Bits 8:11 - 11:8] Number of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed

pub fn reset(&self) -> RESETR

Bit 7 - 7:7] RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when reset takes effect

pub fn reserved3(&self) -> RESERVED3R

Bits 3:6 - 6:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn rtc_4khz_en(&self) -> RTC_4KHZ_ENR

Bit 2 - 2:2] RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN)

pub fn rtc_upd_en(&self) -> RTC_UPD_ENR

Bit 1 - 1:1] RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2 0: RTC_UPD signal is forced to 0 1: RTC_UPD signal is toggling @16 kHz

pub fn en(&self) -> ENR

Bit 0 - 0:0] Enable RTC counter 0: Halted (frozen) 1: Running