Struct cc13x2_cc26x2_hal::aon_pmctl::resetctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn sysreset(&self) -> SYSRESETR

Bit 31 - 31:31] Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again. 0: No effect 1: Generate system reset. Appears as SYSRESET in RESET_SRC

pub fn reserved26(&self) -> RESERVED26R

Bits 26:30 - 30:26] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn boot_det_1_clr(&self) -> BOOT_DET_1_CLRR

Bit 25 - 25:25] Internal. Only to be used through TI provided API.

pub fn boot_det_0_clr(&self) -> BOOT_DET_0_CLRR

Bit 24 - 24:24] Internal. Only to be used through TI provided API.

pub fn reserved18(&self) -> RESERVED18R

Bits 18:23 - 23:18] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn boot_det_1_set(&self) -> BOOT_DET_1_SETR

Bit 17 - 17:17] Internal. Only to be used through TI provided API.

pub fn boot_det_0_set(&self) -> BOOT_DET_0_SETR

Bit 16 - 16:16] Internal. Only to be used through TI provided API.

pub fn wu_from_sd(&self) -> WU_FROM_SDR

Bit 15 - 15:15] A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low) Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources. 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 1: A wakeup has occurred from SHUTDOWN Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.

pub fn gpio_wu_from_sd(&self) -> GPIO_WU_FROM_SDR

Bit 14 - 14:14] A wakeup from SHUTDOWN on an IO event has occurred Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources. 0: The wakeup did not occur from SHUTDOWN on an IO event 1: A wakeup from SHUTDOWN occurred from an IO event The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well. Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.

pub fn boot_det_1(&self) -> BOOT_DET_1R

Bit 13 - 13:13] Internal. Only to be used through TI provided API.

pub fn boot_det_0(&self) -> BOOT_DET_0R

Bit 12 - 12:12] Internal. Only to be used through TI provided API.

pub fn reserved9(&self) -> RESERVED9R

Bits 9:11 - 11:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn vdds_loss_en(&self) -> VDDS_LOSS_ENR

Bit 8 - 8:8] Controls reset generation in case VDDS is lost 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out detect of VDDS generates system reset

pub fn vddr_loss_en(&self) -> VDDR_LOSS_ENR

Bit 7 - 7:7] Controls reset generation in case VDDR is lost 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out detect of VDDR generates system reset

pub fn vdd_loss_en(&self) -> VDD_LOSS_ENR

Bit 6 - 6:6] Controls reset generation in case VDD is lost 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect of VDD generates system reset

pub fn clk_loss_en(&self) -> CLK_LOSS_ENR

Bit 5 - 5:5] Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 0: Clock loss is ignored 1: Clock loss generates system reset Note: Clock loss reset generation must be disabled when changing clock source for SCLK_LF. Failure to do so may result in a spurious system reset. Clock loss reset generation is controlled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]

pub fn mcu_warm_reset(&self) -> MCU_WARM_RESETR

Bit 4 - 4:4] Internal. Only to be used through TI provided API.

pub fn reset_src(&self) -> RESET_SRCR

Bits 1:3 - 3:1] Shows the root cause of the last system reset. More than the reported reset source can have been active during the last system reset but only the root cause is reported. The capture feature is not rearmed until all off the possible reset sources have been released and the result has been copied to AON_PMCTL. During the copy and rearm process it is one 2MHz period in which and eventual new system reset will be reported as Power on reset regardless of the root cause.

pub fn reserved0(&self) -> RESERVED0R

Bit 0 - 0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.