1#![doc = "Peripheral access API for CC2652 microcontrollers (generated using svd2rust v0.14.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.14.0/svd2rust/#peripheral-api"]
2#![deny(missing_docs)]
3#![deny(warnings)]
4#![allow(non_camel_case_types)]
5#![no_std]
6extern crate bare_metal;
7extern crate cortex_m;
8#[cfg(feature = "rt")]
9extern crate cortex_m_rt;
10extern crate vcell;
11use core::marker::PhantomData;
12use core::ops::Deref;
13#[doc = r" Number available in the NVIC for configuring priority"]
14pub const NVIC_PRIO_BITS: u8 = 3;
15#[cfg(feature = "rt")]
16extern "C" {}
17#[doc(hidden)]
18pub union Vector {
19 _handler: unsafe extern "C" fn(),
20 _reserved: u32,
21}
22#[cfg(feature = "rt")]
23#[doc(hidden)]
24#[link_section = ".vector_table.interrupts"]
25#[no_mangle]
26pub static __INTERRUPTS: [Vector; 0] = [];
27#[doc = r" Enumeration of all the interrupts"]
28pub enum Interrupt {}
29unsafe impl ::bare_metal::Nr for Interrupt {
30 #[inline]
31 fn nr(&self) -> u8 {
32 match *self {}
33 }
34}
35#[cfg(feature = "rt")]
36pub use self::Interrupt as interrupt;
37pub use cortex_m::peripheral::Peripherals as CorePeripherals;
38pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
39#[cfg(feature = "rt")]
40pub use cortex_m_rt::interrupt;
41#[doc = "Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic)"]
42pub struct AUX_ADI4 {
43 _marker: PhantomData<*const ()>,
44}
45unsafe impl Send for AUX_ADI4 {}
46impl AUX_ADI4 {
47 #[doc = r" Returns a pointer to the register block"]
48 pub fn ptr() -> *const aux_adi4::RegisterBlock {
49 1074573312 as *const _
50 }
51}
52impl Deref for AUX_ADI4 {
53 type Target = aux_adi4::RegisterBlock;
54 fn deref(&self) -> &aux_adi4::RegisterBlock {
55 unsafe { &*AUX_ADI4::ptr() }
56 }
57}
58#[doc = "Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic)"]
59pub mod aux_adi4;
60#[doc = "Always On (AON) Battery And Temperature MONitor (BATMON) residing in the AON domain Note: This module only supports 32 bit Read/Write access from MCU."]
61pub struct AON_BATMON {
62 _marker: PhantomData<*const ()>,
63}
64unsafe impl Send for AON_BATMON {}
65impl AON_BATMON {
66 #[doc = r" Returns a pointer to the register block"]
67 pub fn ptr() -> *const aon_batmon::RegisterBlock {
68 1074352128 as *const _
69 }
70}
71impl Deref for AON_BATMON {
72 type Target = aon_batmon::RegisterBlock;
73 fn deref(&self) -> &aon_batmon::RegisterBlock {
74 unsafe { &*AON_BATMON::ptr() }
75 }
76}
77#[doc = "Always On (AON) Battery And Temperature MONitor (BATMON) residing in the AON domain Note: This module only supports 32 bit Read/Write access from MCU."]
78pub mod aon_batmon;
79#[doc = "This module configures the event fabric located in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU"]
80pub struct AON_EVENT {
81 _marker: PhantomData<*const ()>,
82}
83unsafe impl Send for AON_EVENT {}
84impl AON_EVENT {
85 #[doc = r" Returns a pointer to the register block"]
86 pub fn ptr() -> *const aon_event::RegisterBlock {
87 1074343936 as *const _
88 }
89}
90impl Deref for AON_EVENT {
91 type Target = aon_event::RegisterBlock;
92 fn deref(&self) -> &aon_event::RegisterBlock {
93 unsafe { &*AON_EVENT::ptr() }
94 }
95}
96#[doc = "This module configures the event fabric located in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU"]
97pub mod aon_event;
98#[doc = "Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain. Note: This module only supports 32 bit Read/Write access from MCU."]
99pub struct AON_IOC {
100 _marker: PhantomData<*const ()>,
101}
102unsafe impl Send for AON_IOC {}
103impl AON_IOC {
104 #[doc = r" Returns a pointer to the register block"]
105 pub fn ptr() -> *const aon_ioc::RegisterBlock {
106 1074348032 as *const _
107 }
108}
109impl Deref for AON_IOC {
110 type Target = aon_ioc::RegisterBlock;
111 fn deref(&self) -> &aon_ioc::RegisterBlock {
112 unsafe { &*AON_IOC::ptr() }
113 }
114}
115#[doc = "Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain. Note: This module only supports 32 bit Read/Write access from MCU."]
116pub mod aon_ioc;
117#[doc = "This component control the Power Management controller residing in the AON domain. Note: This module is only supporting 32 bit Read Write access from MCU"]
118pub struct AON_PMCTL {
119 _marker: PhantomData<*const ()>,
120}
121unsafe impl Send for AON_PMCTL {}
122impl AON_PMCTL {
123 #[doc = r" Returns a pointer to the register block"]
124 pub fn ptr() -> *const aon_pmctl::RegisterBlock {
125 1074331648 as *const _
126 }
127}
128impl Deref for AON_PMCTL {
129 type Target = aon_pmctl::RegisterBlock;
130 fn deref(&self) -> &aon_pmctl::RegisterBlock {
131 unsafe { &*AON_PMCTL::ptr() }
132 }
133}
134#[doc = "This component control the Power Management controller residing in the AON domain. Note: This module is only supporting 32 bit Read Write access from MCU"]
135pub mod aon_pmctl;
136#[doc = "This component control the Real Time Clock residing in AON Note: This module is only supporting 32 bit ReadWrite access."]
137pub struct AON_RTC {
138 _marker: PhantomData<*const ()>,
139}
140unsafe impl Send for AON_RTC {}
141impl AON_RTC {
142 #[doc = r" Returns a pointer to the register block"]
143 pub fn ptr() -> *const aon_rtc::RegisterBlock {
144 1074339840 as *const _
145 }
146}
147impl Deref for AON_RTC {
148 type Target = aon_rtc::RegisterBlock;
149 fn deref(&self) -> &aon_rtc::RegisterBlock {
150 unsafe { &*AON_RTC::ptr() }
151 }
152}
153#[doc = "This component control the Real Time Clock residing in AON Note: This module is only supporting 32 bit ReadWrite access."]
154pub mod aon_rtc;
155#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
156pub struct AUX_AIODIO0 {
157 _marker: PhantomData<*const ()>,
158}
159unsafe impl Send for AUX_AIODIO0 {}
160impl AUX_AIODIO0 {
161 #[doc = r" Returns a pointer to the register block"]
162 pub fn ptr() -> *const aux_aiodio0::RegisterBlock {
163 1074577408 as *const _
164 }
165}
166impl Deref for AUX_AIODIO0 {
167 type Target = aux_aiodio0::RegisterBlock;
168 fn deref(&self) -> &aux_aiodio0::RegisterBlock {
169 unsafe { &*AUX_AIODIO0::ptr() }
170 }
171}
172#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
173pub mod aux_aiodio0;
174#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
175pub struct AUX_AIODIO1 {
176 _marker: PhantomData<*const ()>,
177}
178unsafe impl Send for AUX_AIODIO1 {}
179impl AUX_AIODIO1 {
180 #[doc = r" Returns a pointer to the register block"]
181 pub fn ptr() -> *const aux_aiodio1::RegisterBlock {
182 1074581504 as *const _
183 }
184}
185impl Deref for AUX_AIODIO1 {
186 type Target = aux_aiodio1::RegisterBlock;
187 fn deref(&self) -> &aux_aiodio1::RegisterBlock {
188 unsafe { &*AUX_AIODIO1::ptr() }
189 }
190}
191#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
192pub mod aux_aiodio1;
193#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
194pub struct AUX_AIODIO2 {
195 _marker: PhantomData<*const ()>,
196}
197unsafe impl Send for AUX_AIODIO2 {}
198impl AUX_AIODIO2 {
199 #[doc = r" Returns a pointer to the register block"]
200 pub fn ptr() -> *const aux_aiodio2::RegisterBlock {
201 1074585600 as *const _
202 }
203}
204impl Deref for AUX_AIODIO2 {
205 type Target = aux_aiodio2::RegisterBlock;
206 fn deref(&self) -> &aux_aiodio2::RegisterBlock {
207 unsafe { &*AUX_AIODIO2::ptr() }
208 }
209}
210#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
211pub mod aux_aiodio2;
212#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
213pub struct AUX_AIODIO3 {
214 _marker: PhantomData<*const ()>,
215}
216unsafe impl Send for AUX_AIODIO3 {}
217impl AUX_AIODIO3 {
218 #[doc = r" Returns a pointer to the register block"]
219 pub fn ptr() -> *const aux_aiodio3::RegisterBlock {
220 1074589696 as *const _
221 }
222}
223impl Deref for AUX_AIODIO3 {
224 type Target = aux_aiodio3::RegisterBlock;
225 fn deref(&self) -> &aux_aiodio3::RegisterBlock {
226 unsafe { &*AUX_AIODIO3::ptr() }
227 }
228}
229#[doc = "AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO\\[n\\] does not map to DIO\\[n\\]. AUXIO-DIO remapping is handled by Sensor Controller Studio."]
230pub mod aux_aiodio3;
231#[doc = "AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets AUX_SCE, UDMA0, and system CPU: -Trigger ADC sample and conversion process. - Write ADC samples to FIFO. - Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information. - Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes. To use: - ADC : AUX_SCE must request active operational mode with AON_PMCTL:AUXSCECLK.SRC set to SCLK_HFDIV2. There are no requirements for system CPU. - ISRC : AUX_SCE must request active operational mode. There are no requirements for system CPU. - DAC : AUX_SCE must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to SCE_RATE as long as DAC state machine generates the sample clock. System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information."]
232pub struct AUX_ANAIF {
233 _marker: PhantomData<*const ()>,
234}
235unsafe impl Send for AUX_ANAIF {}
236impl AUX_ANAIF {
237 #[doc = r" Returns a pointer to the register block"]
238 pub fn ptr() -> *const aux_anaif::RegisterBlock {
239 1074565120 as *const _
240 }
241}
242impl Deref for AUX_ANAIF {
243 type Target = aux_anaif::RegisterBlock;
244 fn deref(&self) -> &aux_anaif::RegisterBlock {
245 unsafe { &*AUX_ANAIF::ptr() }
246 }
247}
248#[doc = "AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets AUX_SCE, UDMA0, and system CPU: -Trigger ADC sample and conversion process. - Write ADC samples to FIFO. - Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information. - Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes. To use: - ADC : AUX_SCE must request active operational mode with AON_PMCTL:AUXSCECLK.SRC set to SCLK_HFDIV2. There are no requirements for system CPU. - ISRC : AUX_SCE must request active operational mode. There are no requirements for system CPU. - DAC : AUX_SCE must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to SCE_RATE as long as DAC state machine generates the sample clock. System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information."]
249pub mod aux_anaif;
250#[doc = "AUX Event Controller (AUX_EVCTL) assembles events originating from: - AUX submodules, including ADC and comparators. - AUXIO. - EVENT. - AON_PMCTL. - AON_RTC. - AON_BATMON. into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized. The subscribers to the synchronous event bus are AUX_TIMER01, AUX_SCE and AUX_EVCTL. The subscribers to the asynchronous event bus are AUX_TIMER2, AUX_ANAIF, AUX_TDC and AUX_SYSIF. AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT, as well as to AUX_SCE. AUX_SCE can poll event status registers and combine certain instructions like WEV0, WEV1 with one or two configurable events. The latter saves power when execution must stall until a condition is met."]
251pub struct AUX_EVCTL {
252 _marker: PhantomData<*const ()>,
253}
254unsafe impl Send for AUX_EVCTL {}
255impl AUX_EVCTL {
256 #[doc = r" Returns a pointer to the register block"]
257 pub fn ptr() -> *const aux_evctl::RegisterBlock {
258 1074548736 as *const _
259 }
260}
261impl Deref for AUX_EVCTL {
262 type Target = aux_evctl::RegisterBlock;
263 fn deref(&self) -> &aux_evctl::RegisterBlock {
264 unsafe { &*AUX_EVCTL::ptr() }
265 }
266}
267#[doc = "AUX Event Controller (AUX_EVCTL) assembles events originating from: - AUX submodules, including ADC and comparators. - AUXIO. - EVENT. - AON_PMCTL. - AON_RTC. - AON_BATMON. into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized. The subscribers to the synchronous event bus are AUX_TIMER01, AUX_SCE and AUX_EVCTL. The subscribers to the asynchronous event bus are AUX_TIMER2, AUX_ANAIF, AUX_TDC and AUX_SYSIF. AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT, as well as to AUX_SCE. AUX_SCE can poll event status registers and combine certain instructions like WEV0, WEV1 with one or two configurable events. The latter saves power when execution must stall until a condition is met."]
268pub mod aux_evctl;
269#[doc = "The AUX Multiply-Accumulate (AUX_MAC) peripheral enables AUX_SCE with power-efficient and flexible mathematical operations: - 2's complement signed and unsigned sequential multiplication (MUL) with optional accumulation of the result (MAC). - 16 or 32-bit 2's complement signed and unsigned addition of configurable term and accumulator (ADD). - Results of ADD, MUL and MAC operations are always stored in the accumulator (ACC). Software can easily: - Access arbitrary 16-bit slice of the 40-bit accumulator. - Find the number of leading zero or sign bits. - Perform shift operations on the accumulator. AUX_SCE must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to SCE_RATE to access and use AUX_MAC. System CPU must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to BUS_RATE to access and use AUX_MAC. This guarantees constant execution times for ADD, MUL, and MAC operations. The ADD operation requires a single peripheral clock cycle to finish. MUL and MAC operations require four peripheral clock periods to finish. An unfinished ADD, MUL, or MAC operation stalls register access to this peripheral. AUX_SCE becomes clock gated if it encounters a bus stall. Software can use this to reduce power consumption during back to back accesses. Only full word access is supported by the peripheral. An attempt to write a single byte will have no effect."]
270pub struct AUX_MAC {
271 _marker: PhantomData<*const ()>,
272}
273unsafe impl Send for AUX_MAC {}
274impl AUX_MAC {
275 #[doc = r" Returns a pointer to the register block"]
276 pub fn ptr() -> *const aux_mac::RegisterBlock {
277 1074536448 as *const _
278 }
279}
280impl Deref for AUX_MAC {
281 type Target = aux_mac::RegisterBlock;
282 fn deref(&self) -> &aux_mac::RegisterBlock {
283 unsafe { &*AUX_MAC::ptr() }
284 }
285}
286#[doc = "The AUX Multiply-Accumulate (AUX_MAC) peripheral enables AUX_SCE with power-efficient and flexible mathematical operations: - 2's complement signed and unsigned sequential multiplication (MUL) with optional accumulation of the result (MAC). - 16 or 32-bit 2's complement signed and unsigned addition of configurable term and accumulator (ADD). - Results of ADD, MUL and MAC operations are always stored in the accumulator (ACC). Software can easily: - Access arbitrary 16-bit slice of the 40-bit accumulator. - Find the number of leading zero or sign bits. - Perform shift operations on the accumulator. AUX_SCE must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to SCE_RATE to access and use AUX_MAC. System CPU must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to BUS_RATE to access and use AUX_MAC. This guarantees constant execution times for ADD, MUL, and MAC operations. The ADD operation requires a single peripheral clock cycle to finish. MUL and MAC operations require four peripheral clock periods to finish. An unfinished ADD, MUL, or MAC operation stalls register access to this peripheral. AUX_SCE becomes clock gated if it encounters a bus stall. Software can use this to reduce power consumption during back to back accesses. Only full word access is supported by the peripheral. An attempt to write a single byte will have no effect."]
287pub mod aux_mac;
288#[doc = "AUX Sensor Control Engine (AUX_SCE) is a RISC-style microprocessor with separate fetch and execution cycles. It is optimized for low power and simple operations. AUX_SCE code and data segments are stored in AUX_RAM. AON_PMCTL:AUXSCECLK sets the operational frequency."]
289pub struct AUX_SCE {
290 _marker: PhantomData<*const ()>,
291}
292unsafe impl Send for AUX_SCE {}
293impl AUX_SCE {
294 #[doc = r" Returns a pointer to the register block"]
295 pub fn ptr() -> *const aux_sce::RegisterBlock {
296 1074663424 as *const _
297 }
298}
299impl Deref for AUX_SCE {
300 type Target = aux_sce::RegisterBlock;
301 fn deref(&self) -> &aux_sce::RegisterBlock {
302 unsafe { &*AUX_SCE::ptr() }
303 }
304}
305#[doc = "AUX Sensor Control Engine (AUX_SCE) is a RISC-style microprocessor with separate fetch and execution cycles. It is optimized for low power and simple operations. AUX_SCE code and data segments are stored in AUX_RAM. AON_PMCTL:AUXSCECLK sets the operational frequency."]
306pub mod aux_sce;
307#[doc = "AUX Semaphore (AUX_SMPH) provides hardware means to share modules in AUX safely between CPUs based on resource ownership. AUX_SMPH operates at AUX bus rate."]
308pub struct AUX_SMPH {
309 _marker: PhantomData<*const ()>,
310}
311unsafe impl Send for AUX_SMPH {}
312impl AUX_SMPH {
313 #[doc = r" Returns a pointer to the register block"]
314 pub fn ptr() -> *const aux_smph::RegisterBlock {
315 1074561024 as *const _
316 }
317}
318impl Deref for AUX_SMPH {
319 type Target = aux_smph::RegisterBlock;
320 fn deref(&self) -> &aux_smph::RegisterBlock {
321 unsafe { &*AUX_SMPH::ptr() }
322 }
323}
324#[doc = "AUX Semaphore (AUX_SMPH) provides hardware means to share modules in AUX safely between CPUs based on resource ownership. AUX_SMPH operates at AUX bus rate."]
325pub mod aux_smph;
326#[doc = "The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication. It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete. Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus. AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers. AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency. AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission."]
327pub struct AUX_SPIM {
328 _marker: PhantomData<*const ()>,
329}
330unsafe impl Send for AUX_SPIM {}
331impl AUX_SPIM {
332 #[doc = r" Returns a pointer to the register block"]
333 pub fn ptr() -> *const aux_spim::RegisterBlock {
334 1074532352 as *const _
335 }
336}
337impl Deref for AUX_SPIM {
338 type Target = aux_spim::RegisterBlock;
339 fn deref(&self) -> &aux_spim::RegisterBlock {
340 unsafe { &*AUX_SPIM::ptr() }
341 }
342}
343#[doc = "The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication. It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete. Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus. AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers. AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency. AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission."]
344pub mod aux_spim;
345#[doc = "AUX System Interface (AUX_SYSIF) is responsible for: - system resource requests, such as power supply, clock and, wakeup requests. - configuration of AUX peripheral operational rates for AUX_SPIM, AUX_MAC, AUX_ANAIF DAC state machine and AUX_TIMER01. - configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3. - configuration of AUX_SCE wakeup vectors that trigger AUX_SCE execution from sleep. Peripheral operational rate for AUX modules mentioned above can either be: - SCE rate, which is configured in AON_PMCTL:AUXSCECLK. - AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active. AUX_SYSIF also interfaces AON_RTC and AON_BATMON to enable read access to data and sub-second increment control of AON_RTC."]
346pub struct AUX_SYSIF {
347 _marker: PhantomData<*const ()>,
348}
349unsafe impl Send for AUX_SYSIF {}
350impl AUX_SYSIF {
351 #[doc = r" Returns a pointer to the register block"]
352 pub fn ptr() -> *const aux_sysif::RegisterBlock {
353 1074552832 as *const _
354 }
355}
356impl Deref for AUX_SYSIF {
357 type Target = aux_sysif::RegisterBlock;
358 fn deref(&self) -> &aux_sysif::RegisterBlock {
359 unsafe { &*AUX_SYSIF::ptr() }
360 }
361}
362#[doc = "AUX System Interface (AUX_SYSIF) is responsible for: - system resource requests, such as power supply, clock and, wakeup requests. - configuration of AUX peripheral operational rates for AUX_SPIM, AUX_MAC, AUX_ANAIF DAC state machine and AUX_TIMER01. - configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3. - configuration of AUX_SCE wakeup vectors that trigger AUX_SCE execution from sleep. Peripheral operational rate for AUX modules mentioned above can either be: - SCE rate, which is configured in AON_PMCTL:AUXSCECLK. - AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active. AUX_SYSIF also interfaces AON_RTC and AON_BATMON to enable read access to data and sub-second increment control of AON_RTC."]
363pub mod aux_sysif;
364#[doc = "AUX Time To Digital Converter (AUX_TDC) is used to measure the time between two events with high resolution. AUX_TDC consists of a state machine that operates at AUX bus rate and an asynchronous fast-counter which is clocked by the TDC clock. DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL configures TDC clock source. The fast-counter counts on both edges of the TDC clock to double the resolution. See the Technical Reference Manual for event timing requirements."]
365pub struct AUX_TDC {
366 _marker: PhantomData<*const ()>,
367}
368unsafe impl Send for AUX_TDC {}
369impl AUX_TDC {
370 #[doc = r" Returns a pointer to the register block"]
371 pub fn ptr() -> *const aux_tdc::RegisterBlock {
372 1074544640 as *const _
373 }
374}
375impl Deref for AUX_TDC {
376 type Target = aux_tdc::RegisterBlock;
377 fn deref(&self) -> &aux_tdc::RegisterBlock {
378 unsafe { &*AUX_TDC::ptr() }
379 }
380}
381#[doc = "AUX Time To Digital Converter (AUX_TDC) is used to measure the time between two events with high resolution. AUX_TDC consists of a state machine that operates at AUX bus rate and an asynchronous fast-counter which is clocked by the TDC clock. DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL configures TDC clock source. The fast-counter counts on both edges of the TDC clock to double the resolution. See the Technical Reference Manual for event timing requirements."]
382pub mod aux_tdc;
383#[doc = "AUX Timer 0 and AUX Timer 1 (AUX_TIMER01) are two 16-bit timers capable of generating one event each: - AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV. - AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV. The events are described in T0TARGET and T1TARGET. Subscribers to the AUX event bus can use these events to sequence and trigger actions. AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the peripheral clock frequency used by the prescaler, timer, and event logic to SCE or AUX bus rate. To use AUX_TIMER01: - AUX_SCE must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to SCE_RATE. - System CPU must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to BUS_RATE. - The timers must only subscribe to events updated at the peripheral clock frequency or lower. Unexpected execution behavior can result if software does not obey these rules."]
384pub struct AUX_TIMER01 {
385 _marker: PhantomData<*const ()>,
386}
387unsafe impl Send for AUX_TIMER01 {}
388impl AUX_TIMER01 {
389 #[doc = r" Returns a pointer to the register block"]
390 pub fn ptr() -> *const aux_timer01::RegisterBlock {
391 1074556928 as *const _
392 }
393}
394impl Deref for AUX_TIMER01 {
395 type Target = aux_timer01::RegisterBlock;
396 fn deref(&self) -> &aux_timer01::RegisterBlock {
397 unsafe { &*AUX_TIMER01::ptr() }
398 }
399}
400#[doc = "AUX Timer 0 and AUX Timer 1 (AUX_TIMER01) are two 16-bit timers capable of generating one event each: - AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV. - AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV. The events are described in T0TARGET and T1TARGET. Subscribers to the AUX event bus can use these events to sequence and trigger actions. AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the peripheral clock frequency used by the prescaler, timer, and event logic to SCE or AUX bus rate. To use AUX_TIMER01: - AUX_SCE must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to SCE_RATE. - System CPU must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to BUS_RATE. - The timers must only subscribe to events updated at the peripheral clock frequency or lower. Unexpected execution behavior can result if software does not obey these rules."]
401pub mod aux_timer01;
402#[doc = "AUX Timer2 (AUX_TIMER2) offers flexible: - generation of waveforms and events. - capture of signal period and duty cycle. - generation of single clock pulse. It consists of a: - 16-bit counter. - 4 capture compare channels. - 4 event outputs, which are mapped to AUX event bus, see EVCTL. Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer."]
403pub struct AUX_TIMER2 {
404 _marker: PhantomData<*const ()>,
405}
406unsafe impl Send for AUX_TIMER2 {}
407impl AUX_TIMER2 {
408 #[doc = r" Returns a pointer to the register block"]
409 pub fn ptr() -> *const aux_timer2::RegisterBlock {
410 1074540544 as *const _
411 }
412}
413impl Deref for AUX_TIMER2 {
414 type Target = aux_timer2::RegisterBlock;
415 fn deref(&self) -> &aux_timer2::RegisterBlock {
416 unsafe { &*AUX_TIMER2::ptr() }
417 }
418}
419#[doc = "AUX Timer2 (AUX_TIMER2) offers flexible: - generation of waveforms and events. - capture of signal period and duty cycle. - generation of single clock pulse. It consists of a: - 16-bit counter. - 4 capture compare channels. - 4 event outputs, which are mapped to AUX event bus, see EVCTL. Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer."]
420pub mod aux_timer2;
421#[doc = "Customer configuration area (CCFG)"]
422pub struct CCFG {
423 _marker: PhantomData<*const ()>,
424}
425unsafe impl Send for CCFG {}
426impl CCFG {
427 #[doc = r" Returns a pointer to the register block"]
428 pub fn ptr() -> *const ccfg::RegisterBlock {
429 1342189568 as *const _
430 }
431}
432impl Deref for CCFG {
433 type Target = ccfg::RegisterBlock;
434 fn deref(&self) -> &ccfg::RegisterBlock {
435 unsafe { &*CCFG::ptr() }
436 }
437}
438#[doc = "Customer configuration area (CCFG)"]
439pub mod ccfg;
440#[doc = "Cortex-M's Data watchpoint and Trace (DWT)"]
441pub struct CPU_DWT {
442 _marker: PhantomData<*const ()>,
443}
444unsafe impl Send for CPU_DWT {}
445impl CPU_DWT {
446 #[doc = r" Returns a pointer to the register block"]
447 pub fn ptr() -> *const cpu_dwt::RegisterBlock {
448 3758100480 as *const _
449 }
450}
451impl Deref for CPU_DWT {
452 type Target = cpu_dwt::RegisterBlock;
453 fn deref(&self) -> &cpu_dwt::RegisterBlock {
454 unsafe { &*CPU_DWT::ptr() }
455 }
456}
457#[doc = "Cortex-M's Data watchpoint and Trace (DWT)"]
458pub mod cpu_dwt;
459#[doc = "Cortex-M's Flash Patch and Breakpoint (FPB)"]
460pub struct CPU_FPB {
461 _marker: PhantomData<*const ()>,
462}
463unsafe impl Send for CPU_FPB {}
464impl CPU_FPB {
465 #[doc = r" Returns a pointer to the register block"]
466 pub fn ptr() -> *const cpu_fpb::RegisterBlock {
467 3758104576 as *const _
468 }
469}
470impl Deref for CPU_FPB {
471 type Target = cpu_fpb::RegisterBlock;
472 fn deref(&self) -> &cpu_fpb::RegisterBlock {
473 unsafe { &*CPU_FPB::ptr() }
474 }
475}
476#[doc = "Cortex-M's Flash Patch and Breakpoint (FPB)"]
477pub mod cpu_fpb;
478#[doc = "Cortex-M's Instrumentation Trace Macrocell (ITM)"]
479pub struct CPU_ITM {
480 _marker: PhantomData<*const ()>,
481}
482unsafe impl Send for CPU_ITM {}
483impl CPU_ITM {
484 #[doc = r" Returns a pointer to the register block"]
485 pub fn ptr() -> *const cpu_itm::RegisterBlock {
486 3758096384 as *const _
487 }
488}
489impl Deref for CPU_ITM {
490 type Target = cpu_itm::RegisterBlock;
491 fn deref(&self) -> &cpu_itm::RegisterBlock {
492 unsafe { &*CPU_ITM::ptr() }
493 }
494}
495#[doc = "Cortex-M's Instrumentation Trace Macrocell (ITM)"]
496pub mod cpu_itm;
497#[doc = "Cortex-M's System Control Space (SCS)"]
498pub struct CPU_SCS {
499 _marker: PhantomData<*const ()>,
500}
501unsafe impl Send for CPU_SCS {}
502impl CPU_SCS {
503 #[doc = r" Returns a pointer to the register block"]
504 pub fn ptr() -> *const cpu_scs::RegisterBlock {
505 3758153728 as *const _
506 }
507}
508impl Deref for CPU_SCS {
509 type Target = cpu_scs::RegisterBlock;
510 fn deref(&self) -> &cpu_scs::RegisterBlock {
511 unsafe { &*CPU_SCS::ptr() }
512 }
513}
514#[doc = "Cortex-M's System Control Space (SCS)"]
515pub mod cpu_scs;
516#[doc = "Cortex-M's TI proprietary registers"]
517pub struct CPU_TIPROP {
518 _marker: PhantomData<*const ()>,
519}
520unsafe impl Send for CPU_TIPROP {}
521impl CPU_TIPROP {
522 #[doc = r" Returns a pointer to the register block"]
523 pub fn ptr() -> *const cpu_tiprop::RegisterBlock {
524 3759136768 as *const _
525 }
526}
527impl Deref for CPU_TIPROP {
528 type Target = cpu_tiprop::RegisterBlock;
529 fn deref(&self) -> &cpu_tiprop::RegisterBlock {
530 unsafe { &*CPU_TIPROP::ptr() }
531 }
532}
533#[doc = "Cortex-M's TI proprietary registers"]
534pub mod cpu_tiprop;
535#[doc = "Cortex-M's Trace Port Interface Unit (TPIU)"]
536pub struct CPU_TPIU {
537 _marker: PhantomData<*const ()>,
538}
539unsafe impl Send for CPU_TPIU {}
540impl CPU_TPIU {
541 #[doc = r" Returns a pointer to the register block"]
542 pub fn ptr() -> *const cpu_tpiu::RegisterBlock {
543 3758358528 as *const _
544 }
545}
546impl Deref for CPU_TPIU {
547 type Target = cpu_tpiu::RegisterBlock;
548 fn deref(&self) -> &cpu_tpiu::RegisterBlock {
549 unsafe { &*CPU_TPIU::ptr() }
550 }
551}
552#[doc = "Cortex-M's Trace Port Interface Unit (TPIU)"]
553pub mod cpu_tpiu;
554#[doc = "DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage."]
555pub struct CRYPTO {
556 _marker: PhantomData<*const ()>,
557}
558unsafe impl Send for CRYPTO {}
559impl CRYPTO {
560 #[doc = r" Returns a pointer to the register block"]
561 pub fn ptr() -> *const crypto::RegisterBlock {
562 1073889280 as *const _
563 }
564}
565impl Deref for CRYPTO {
566 type Target = crypto::RegisterBlock;
567 fn deref(&self) -> &crypto::RegisterBlock {
568 unsafe { &*CRYPTO::ptr() }
569 }
570}
571#[doc = "DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage."]
572pub mod crypto;
573#[doc = "This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated."]
574pub struct AUX_DDI0_OSC {
575 _marker: PhantomData<*const ()>,
576}
577unsafe impl Send for AUX_DDI0_OSC {}
578impl AUX_DDI0_OSC {
579 #[doc = r" Returns a pointer to the register block"]
580 pub fn ptr() -> *const aux_ddi0_osc::RegisterBlock {
581 1074569216 as *const _
582 }
583}
584impl Deref for AUX_DDI0_OSC {
585 type Target = aux_ddi0_osc::RegisterBlock;
586 fn deref(&self) -> &aux_ddi0_osc::RegisterBlock {
587 unsafe { &*AUX_DDI0_OSC::ptr() }
588 }
589}
590#[doc = "This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated."]
591pub mod aux_ddi0_osc;
592#[doc = "Event Fabric Component Definition"]
593pub struct EVENT {
594 _marker: PhantomData<*const ()>,
595}
596unsafe impl Send for EVENT {}
597impl EVENT {
598 #[doc = r" Returns a pointer to the register block"]
599 pub fn ptr() -> *const event::RegisterBlock {
600 1074278400 as *const _
601 }
602}
603impl Deref for EVENT {
604 type Target = event::RegisterBlock;
605 fn deref(&self) -> &event::RegisterBlock {
606 unsafe { &*EVENT::ptr() }
607 }
608}
609#[doc = "Event Fabric Component Definition"]
610pub mod event;
611#[doc = "Factory configuration area (FCFG1)"]
612pub struct FCFG1 {
613 _marker: PhantomData<*const ()>,
614}
615unsafe impl Send for FCFG1 {}
616impl FCFG1 {
617 #[doc = r" Returns a pointer to the register block"]
618 pub fn ptr() -> *const fcfg1::RegisterBlock {
619 1342181376 as *const _
620 }
621}
622impl Deref for FCFG1 {
623 type Target = fcfg1::RegisterBlock;
624 fn deref(&self) -> &fcfg1::RegisterBlock {
625 unsafe { &*FCFG1::ptr() }
626 }
627}
628#[doc = "Factory configuration area (FCFG1)"]
629pub mod fcfg1;
630#[doc = "Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM."]
631pub struct FLASH {
632 _marker: PhantomData<*const ()>,
633}
634unsafe impl Send for FLASH {}
635impl FLASH {
636 #[doc = r" Returns a pointer to the register block"]
637 pub fn ptr() -> *const flash::RegisterBlock {
638 1073938432 as *const _
639 }
640}
641impl Deref for FLASH {
642 type Target = flash::RegisterBlock;
643 fn deref(&self) -> &flash::RegisterBlock {
644 unsafe { &*FLASH::ptr() }
645 }
646}
647#[doc = "Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM."]
648pub mod flash;
649#[doc = "MCU GPIO - I/F for controlling and reading IO status and IO event status"]
650pub struct GPIO {
651 _marker: PhantomData<*const ()>,
652}
653unsafe impl Send for GPIO {}
654impl GPIO {
655 #[doc = r" Returns a pointer to the register block"]
656 pub fn ptr() -> *const gpio::RegisterBlock {
657 1073881088 as *const _
658 }
659}
660impl Deref for GPIO {
661 type Target = gpio::RegisterBlock;
662 fn deref(&self) -> &gpio::RegisterBlock {
663 unsafe { &*GPIO::ptr() }
664 }
665}
666#[doc = "MCU GPIO - I/F for controlling and reading IO status and IO event status"]
667pub mod gpio;
668#[doc = "General Purpose Timer."]
669pub struct GPT0 {
670 _marker: PhantomData<*const ()>,
671}
672unsafe impl Send for GPT0 {}
673impl GPT0 {
674 #[doc = r" Returns a pointer to the register block"]
675 pub fn ptr() -> *const gpt0::RegisterBlock {
676 1073807360 as *const _
677 }
678}
679impl Deref for GPT0 {
680 type Target = gpt0::RegisterBlock;
681 fn deref(&self) -> &gpt0::RegisterBlock {
682 unsafe { &*GPT0::ptr() }
683 }
684}
685#[doc = "General Purpose Timer."]
686pub mod gpt0;
687#[doc = "General Purpose Timer."]
688pub struct GPT1 {
689 _marker: PhantomData<*const ()>,
690}
691unsafe impl Send for GPT1 {}
692impl GPT1 {
693 #[doc = r" Returns a pointer to the register block"]
694 pub fn ptr() -> *const gpt1::RegisterBlock {
695 1073811456 as *const _
696 }
697}
698impl Deref for GPT1 {
699 type Target = gpt1::RegisterBlock;
700 fn deref(&self) -> &gpt1::RegisterBlock {
701 unsafe { &*GPT1::ptr() }
702 }
703}
704#[doc = "General Purpose Timer."]
705pub mod gpt1;
706#[doc = "General Purpose Timer."]
707pub struct GPT2 {
708 _marker: PhantomData<*const ()>,
709}
710unsafe impl Send for GPT2 {}
711impl GPT2 {
712 #[doc = r" Returns a pointer to the register block"]
713 pub fn ptr() -> *const gpt2::RegisterBlock {
714 1073815552 as *const _
715 }
716}
717impl Deref for GPT2 {
718 type Target = gpt2::RegisterBlock;
719 fn deref(&self) -> &gpt2::RegisterBlock {
720 unsafe { &*GPT2::ptr() }
721 }
722}
723#[doc = "General Purpose Timer."]
724pub mod gpt2;
725#[doc = "General Purpose Timer."]
726pub struct GPT3 {
727 _marker: PhantomData<*const ()>,
728}
729unsafe impl Send for GPT3 {}
730impl GPT3 {
731 #[doc = r" Returns a pointer to the register block"]
732 pub fn ptr() -> *const gpt3::RegisterBlock {
733 1073819648 as *const _
734 }
735}
736impl Deref for GPT3 {
737 type Target = gpt3::RegisterBlock;
738 fn deref(&self) -> &gpt3::RegisterBlock {
739 unsafe { &*GPT3::ptr() }
740 }
741}
742#[doc = "General Purpose Timer."]
743pub mod gpt3;
744#[doc = "I2CMaster/Slave Serial Controler"]
745pub struct I2C0 {
746 _marker: PhantomData<*const ()>,
747}
748unsafe impl Send for I2C0 {}
749impl I2C0 {
750 #[doc = r" Returns a pointer to the register block"]
751 pub fn ptr() -> *const i2c0::RegisterBlock {
752 1073750016 as *const _
753 }
754}
755impl Deref for I2C0 {
756 type Target = i2c0::RegisterBlock;
757 fn deref(&self) -> &i2c0::RegisterBlock {
758 unsafe { &*I2C0::ptr() }
759 }
760}
761#[doc = "I2CMaster/Slave Serial Controler"]
762pub mod i2c0;
763#[doc = "I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP"]
764pub struct I2S0 {
765 _marker: PhantomData<*const ()>,
766}
767unsafe impl Send for I2S0 {}
768impl I2S0 {
769 #[doc = r" Returns a pointer to the register block"]
770 pub fn ptr() -> *const i2s0::RegisterBlock {
771 1073876992 as *const _
772 }
773}
774impl Deref for I2S0 {
775 type Target = i2s0::RegisterBlock;
776 fn deref(&self) -> &i2s0::RegisterBlock {
777 unsafe { &*I2S0::ptr() }
778 }
779}
780#[doc = "I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP"]
781pub mod i2s0;
782#[doc = "IO Controller (IOC) - configures all the DIOs and resides in the MCU domain."]
783pub struct IOC {
784 _marker: PhantomData<*const ()>,
785}
786unsafe impl Send for IOC {}
787impl IOC {
788 #[doc = r" Returns a pointer to the register block"]
789 pub fn ptr() -> *const ioc::RegisterBlock {
790 1074270208 as *const _
791 }
792}
793impl Deref for IOC {
794 type Target = ioc::RegisterBlock;
795 fn deref(&self) -> &ioc::RegisterBlock {
796 unsafe { &*IOC::ptr() }
797 }
798}
799#[doc = "IO Controller (IOC) - configures all the DIOs and resides in the MCU domain."]
800pub mod ioc;
801#[doc = "Integrated module which combines the Public Key Acceleration module, optional True Random Gnerator, optional interrupt controller and a standard bus interface"]
802pub struct PKA {
803 _marker: PhantomData<*const ()>,
804}
805unsafe impl Send for PKA {}
806impl PKA {
807 #[doc = r" Returns a pointer to the register block"]
808 pub fn ptr() -> *const pka::RegisterBlock {
809 1073893376 as *const _
810 }
811}
812impl Deref for PKA {
813 type Target = pka::RegisterBlock;
814 fn deref(&self) -> &pka::RegisterBlock {
815 unsafe { &*PKA::ptr() }
816 }
817}
818#[doc = "Integrated module which combines the Public Key Acceleration module, optional True Random Gnerator, optional interrupt controller and a standard bus interface"]
819pub mod pka;
820#[doc = "Integrated module which includes the PKA K"]
821pub struct PKA_INT {
822 _marker: PhantomData<*const ()>,
823}
824unsafe impl Send for PKA_INT {}
825impl PKA_INT {
826 #[doc = r" Returns a pointer to the register block"]
827 pub fn ptr() -> *const pka_int::RegisterBlock {
828 1073901568 as *const _
829 }
830}
831impl Deref for PKA_INT {
832 type Target = pka_int::RegisterBlock;
833 fn deref(&self) -> &pka_int::RegisterBlock {
834 unsafe { &*PKA_INT::ptr() }
835 }
836}
837#[doc = "Integrated module which includes the PKA K"]
838pub mod pka_int;
839#[doc = "Power, Reset and Clock Management"]
840pub struct PRCM {
841 _marker: PhantomData<*const ()>,
842}
843unsafe impl Send for PRCM {}
844impl PRCM {
845 #[doc = r" Returns a pointer to the register block"]
846 pub fn ptr() -> *const prcm::RegisterBlock {
847 1074274304 as *const _
848 }
849}
850impl Deref for PRCM {
851 type Target = prcm::RegisterBlock;
852 fn deref(&self) -> &prcm::RegisterBlock {
853 unsafe { &*PRCM::ptr() }
854 }
855}
856#[doc = "Power, Reset and Clock Management"]
857pub mod prcm;
858#[doc = "RF core doorbell The doorbell module is the main user interface to the radio sub-system. It contains the registers used for both submitting commands to the radio, and for configuring radio interrupts from the RF core."]
859pub struct RFC_DBELL {
860 _marker: PhantomData<*const ()>,
861}
862unsafe impl Send for RFC_DBELL {}
863impl RFC_DBELL {
864 #[doc = r" Returns a pointer to the register block"]
865 pub fn ptr() -> *const rfc_dbell::RegisterBlock {
866 1074008064 as *const _
867 }
868}
869impl Deref for RFC_DBELL {
870 type Target = rfc_dbell::RegisterBlock;
871 fn deref(&self) -> &rfc_dbell::RegisterBlock {
872 unsafe { &*RFC_DBELL::ptr() }
873 }
874}
875#[doc = "RF core doorbell The doorbell module is the main user interface to the radio sub-system. It contains the registers used for both submitting commands to the radio, and for configuring radio interrupts from the RF core."]
876pub mod rfc_dbell;
877#[doc = "RF core power management This module contains clock control for all RF core sub-modules."]
878pub struct RFC_PWR {
879 _marker: PhantomData<*const ()>,
880}
881unsafe impl Send for RFC_PWR {}
882impl RFC_PWR {
883 #[doc = r" Returns a pointer to the register block"]
884 pub fn ptr() -> *const rfc_pwr::RegisterBlock {
885 1074003968 as *const _
886 }
887}
888impl Deref for RFC_PWR {
889 type Target = rfc_pwr::RegisterBlock;
890 fn deref(&self) -> &rfc_pwr::RegisterBlock {
891 unsafe { &*RFC_PWR::ptr() }
892 }
893}
894#[doc = "RF core power management This module contains clock control for all RF core sub-modules."]
895pub mod rfc_pwr;
896#[doc = "RF core radio timer"]
897pub struct RFC_RAT {
898 _marker: PhantomData<*const ()>,
899}
900unsafe impl Send for RFC_RAT {}
901impl RFC_RAT {
902 #[doc = r" Returns a pointer to the register block"]
903 pub fn ptr() -> *const rfc_rat::RegisterBlock {
904 1074016256 as *const _
905 }
906}
907impl Deref for RFC_RAT {
908 type Target = rfc_rat::RegisterBlock;
909 fn deref(&self) -> &rfc_rat::RegisterBlock {
910 unsafe { &*RFC_RAT::ptr() }
911 }
912}
913#[doc = "RF core radio timer"]
914pub mod rfc_rat;
915#[doc = "MCU Semaphore Module This module provides 32 binary semaphores. The state of a binary semaphore is either taken or available. A semaphore does not implement any ownership attribute. Still, a semaphore can be used to handle mutual exclusion scenarios."]
916pub struct SMPH {
917 _marker: PhantomData<*const ()>,
918}
919unsafe impl Send for SMPH {}
920impl SMPH {
921 #[doc = r" Returns a pointer to the register block"]
922 pub fn ptr() -> *const smph::RegisterBlock {
923 1074282496 as *const _
924 }
925}
926impl Deref for SMPH {
927 type Target = smph::RegisterBlock;
928 fn deref(&self) -> &smph::RegisterBlock {
929 unsafe { &*SMPH::ptr() }
930 }
931}
932#[doc = "MCU Semaphore Module This module provides 32 binary semaphores. The state of a binary semaphore is either taken or available. A semaphore does not implement any ownership attribute. Still, a semaphore can be used to handle mutual exclusion scenarios."]
933pub mod smph;
934#[doc = "General Purpose RAM"]
935pub struct SRAM_MMR {
936 _marker: PhantomData<*const ()>,
937}
938unsafe impl Send for SRAM_MMR {}
939impl SRAM_MMR {
940 #[doc = r" Returns a pointer to the register block"]
941 pub fn ptr() -> *const sram_mmr::RegisterBlock {
942 1073958912 as *const _
943 }
944}
945impl Deref for SRAM_MMR {
946 type Target = sram_mmr::RegisterBlock;
947 fn deref(&self) -> &sram_mmr::RegisterBlock {
948 unsafe { &*SRAM_MMR::ptr() }
949 }
950}
951#[doc = "General Purpose RAM"]
952pub mod sram_mmr;
953#[doc = "Synchronous Serial Interface with master and slave capabilities"]
954pub struct SSI0 {
955 _marker: PhantomData<*const ()>,
956}
957unsafe impl Send for SSI0 {}
958impl SSI0 {
959 #[doc = r" Returns a pointer to the register block"]
960 pub fn ptr() -> *const ssi0::RegisterBlock {
961 1073741824 as *const _
962 }
963}
964impl Deref for SSI0 {
965 type Target = ssi0::RegisterBlock;
966 fn deref(&self) -> &ssi0::RegisterBlock {
967 unsafe { &*SSI0::ptr() }
968 }
969}
970#[doc = "Synchronous Serial Interface with master and slave capabilities"]
971pub mod ssi0;
972#[doc = "Synchronous Serial Interface with master and slave capabilities"]
973pub struct SSI1 {
974 _marker: PhantomData<*const ()>,
975}
976unsafe impl Send for SSI1 {}
977impl SSI1 {
978 #[doc = r" Returns a pointer to the register block"]
979 pub fn ptr() -> *const ssi1::RegisterBlock {
980 1073774592 as *const _
981 }
982}
983impl Deref for SSI1 {
984 type Target = ssi1::RegisterBlock;
985 fn deref(&self) -> &ssi1::RegisterBlock {
986 unsafe { &*SSI1::ptr() }
987 }
988}
989#[doc = "Synchronous Serial Interface with master and slave capabilities"]
990pub mod ssi1;
991#[doc = "True Random Number Generator"]
992pub struct TRNG {
993 _marker: PhantomData<*const ()>,
994}
995unsafe impl Send for TRNG {}
996impl TRNG {
997 #[doc = r" Returns a pointer to the register block"]
998 pub fn ptr() -> *const trng::RegisterBlock {
999 1073905664 as *const _
1000 }
1001}
1002impl Deref for TRNG {
1003 type Target = trng::RegisterBlock;
1004 fn deref(&self) -> &trng::RegisterBlock {
1005 unsafe { &*TRNG::ptr() }
1006 }
1007}
1008#[doc = "True Random Number Generator"]
1009pub mod trng;
1010#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1011pub struct UART0 {
1012 _marker: PhantomData<*const ()>,
1013}
1014unsafe impl Send for UART0 {}
1015impl UART0 {
1016 #[doc = r" Returns a pointer to the register block"]
1017 pub fn ptr() -> *const uart0::RegisterBlock {
1018 1073745920 as *const _
1019 }
1020}
1021impl Deref for UART0 {
1022 type Target = uart0::RegisterBlock;
1023 fn deref(&self) -> &uart0::RegisterBlock {
1024 unsafe { &*UART0::ptr() }
1025 }
1026}
1027#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1028pub mod uart0;
1029#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1030pub struct UART1 {
1031 _marker: PhantomData<*const ()>,
1032}
1033unsafe impl Send for UART1 {}
1034impl UART1 {
1035 #[doc = r" Returns a pointer to the register block"]
1036 pub fn ptr() -> *const uart1::RegisterBlock {
1037 1073786880 as *const _
1038 }
1039}
1040impl Deref for UART1 {
1041 type Target = uart1::RegisterBlock;
1042 fn deref(&self) -> &uart1::RegisterBlock {
1043 unsafe { &*UART1::ptr() }
1044 }
1045}
1046#[doc = "Universal Asynchronous Receiver/Transmitter (UART) interface"]
1047pub mod uart1;
1048#[doc = "ARM Micro Direct Memory Access Controller"]
1049pub struct UDMA0 {
1050 _marker: PhantomData<*const ()>,
1051}
1052unsafe impl Send for UDMA0 {}
1053impl UDMA0 {
1054 #[doc = r" Returns a pointer to the register block"]
1055 pub fn ptr() -> *const udma0::RegisterBlock {
1056 1073872896 as *const _
1057 }
1058}
1059impl Deref for UDMA0 {
1060 type Target = udma0::RegisterBlock;
1061 fn deref(&self) -> &udma0::RegisterBlock {
1062 unsafe { &*UDMA0::ptr() }
1063 }
1064}
1065#[doc = "ARM Micro Direct Memory Access Controller"]
1066pub mod udma0;
1067#[doc = "Versatile Instruction Memory System Controls memory access to the Flash and encapsulates the following instruction memories: - Boot ROM - Cache / GPRAM"]
1068pub struct VIMS {
1069 _marker: PhantomData<*const ()>,
1070}
1071unsafe impl Send for VIMS {}
1072impl VIMS {
1073 #[doc = r" Returns a pointer to the register block"]
1074 pub fn ptr() -> *const vims::RegisterBlock {
1075 1073954816 as *const _
1076 }
1077}
1078impl Deref for VIMS {
1079 type Target = vims::RegisterBlock;
1080 fn deref(&self) -> &vims::RegisterBlock {
1081 unsafe { &*VIMS::ptr() }
1082 }
1083}
1084#[doc = "Versatile Instruction Memory System Controls memory access to the Flash and encapsulates the following instruction memories: - Boot ROM - Cache / GPRAM"]
1085pub mod vims;
1086#[doc = "Watchdog Timer"]
1087pub struct WDT {
1088 _marker: PhantomData<*const ()>,
1089}
1090unsafe impl Send for WDT {}
1091impl WDT {
1092 #[doc = r" Returns a pointer to the register block"]
1093 pub fn ptr() -> *const wdt::RegisterBlock {
1094 1074266112 as *const _
1095 }
1096}
1097impl Deref for WDT {
1098 type Target = wdt::RegisterBlock;
1099 fn deref(&self) -> &wdt::RegisterBlock {
1100 unsafe { &*WDT::ptr() }
1101 }
1102}
1103#[doc = "Watchdog Timer"]
1104pub mod wdt;
1105#[allow(renamed_and_removed_lints)]
1106#[allow(private_no_mangle_statics)]
1107#[no_mangle]
1108static mut DEVICE_PERIPHERALS: bool = false;
1109#[doc = r" All the peripherals"]
1110#[allow(non_snake_case)]
1111pub struct Peripherals {
1112 #[doc = "AUX_ADI4"]
1113 pub AUX_ADI4: AUX_ADI4,
1114 #[doc = "AON_BATMON"]
1115 pub AON_BATMON: AON_BATMON,
1116 #[doc = "AON_EVENT"]
1117 pub AON_EVENT: AON_EVENT,
1118 #[doc = "AON_IOC"]
1119 pub AON_IOC: AON_IOC,
1120 #[doc = "AON_PMCTL"]
1121 pub AON_PMCTL: AON_PMCTL,
1122 #[doc = "AON_RTC"]
1123 pub AON_RTC: AON_RTC,
1124 #[doc = "AUX_AIODIO0"]
1125 pub AUX_AIODIO0: AUX_AIODIO0,
1126 #[doc = "AUX_AIODIO1"]
1127 pub AUX_AIODIO1: AUX_AIODIO1,
1128 #[doc = "AUX_AIODIO2"]
1129 pub AUX_AIODIO2: AUX_AIODIO2,
1130 #[doc = "AUX_AIODIO3"]
1131 pub AUX_AIODIO3: AUX_AIODIO3,
1132 #[doc = "AUX_ANAIF"]
1133 pub AUX_ANAIF: AUX_ANAIF,
1134 #[doc = "AUX_EVCTL"]
1135 pub AUX_EVCTL: AUX_EVCTL,
1136 #[doc = "AUX_MAC"]
1137 pub AUX_MAC: AUX_MAC,
1138 #[doc = "AUX_SCE"]
1139 pub AUX_SCE: AUX_SCE,
1140 #[doc = "AUX_SMPH"]
1141 pub AUX_SMPH: AUX_SMPH,
1142 #[doc = "AUX_SPIM"]
1143 pub AUX_SPIM: AUX_SPIM,
1144 #[doc = "AUX_SYSIF"]
1145 pub AUX_SYSIF: AUX_SYSIF,
1146 #[doc = "AUX_TDC"]
1147 pub AUX_TDC: AUX_TDC,
1148 #[doc = "AUX_TIMER01"]
1149 pub AUX_TIMER01: AUX_TIMER01,
1150 #[doc = "AUX_TIMER2"]
1151 pub AUX_TIMER2: AUX_TIMER2,
1152 #[doc = "CCFG"]
1153 pub CCFG: CCFG,
1154 #[doc = "CPU_DWT"]
1155 pub CPU_DWT: CPU_DWT,
1156 #[doc = "CPU_FPB"]
1157 pub CPU_FPB: CPU_FPB,
1158 #[doc = "CPU_ITM"]
1159 pub CPU_ITM: CPU_ITM,
1160 #[doc = "CPU_SCS"]
1161 pub CPU_SCS: CPU_SCS,
1162 #[doc = "CPU_TIPROP"]
1163 pub CPU_TIPROP: CPU_TIPROP,
1164 #[doc = "CPU_TPIU"]
1165 pub CPU_TPIU: CPU_TPIU,
1166 #[doc = "CRYPTO"]
1167 pub CRYPTO: CRYPTO,
1168 #[doc = "AUX_DDI0_OSC"]
1169 pub AUX_DDI0_OSC: AUX_DDI0_OSC,
1170 #[doc = "EVENT"]
1171 pub EVENT: EVENT,
1172 #[doc = "FCFG1"]
1173 pub FCFG1: FCFG1,
1174 #[doc = "FLASH"]
1175 pub FLASH: FLASH,
1176 #[doc = "GPIO"]
1177 pub GPIO: GPIO,
1178 #[doc = "GPT0"]
1179 pub GPT0: GPT0,
1180 #[doc = "GPT1"]
1181 pub GPT1: GPT1,
1182 #[doc = "GPT2"]
1183 pub GPT2: GPT2,
1184 #[doc = "GPT3"]
1185 pub GPT3: GPT3,
1186 #[doc = "I2C0"]
1187 pub I2C0: I2C0,
1188 #[doc = "I2S0"]
1189 pub I2S0: I2S0,
1190 #[doc = "IOC"]
1191 pub IOC: IOC,
1192 #[doc = "PKA"]
1193 pub PKA: PKA,
1194 #[doc = "PKA_INT"]
1195 pub PKA_INT: PKA_INT,
1196 #[doc = "PRCM"]
1197 pub PRCM: PRCM,
1198 #[doc = "RFC_DBELL"]
1199 pub RFC_DBELL: RFC_DBELL,
1200 #[doc = "RFC_PWR"]
1201 pub RFC_PWR: RFC_PWR,
1202 #[doc = "RFC_RAT"]
1203 pub RFC_RAT: RFC_RAT,
1204 #[doc = "SMPH"]
1205 pub SMPH: SMPH,
1206 #[doc = "SRAM_MMR"]
1207 pub SRAM_MMR: SRAM_MMR,
1208 #[doc = "SSI0"]
1209 pub SSI0: SSI0,
1210 #[doc = "SSI1"]
1211 pub SSI1: SSI1,
1212 #[doc = "TRNG"]
1213 pub TRNG: TRNG,
1214 #[doc = "UART0"]
1215 pub UART0: UART0,
1216 #[doc = "UART1"]
1217 pub UART1: UART1,
1218 #[doc = "UDMA0"]
1219 pub UDMA0: UDMA0,
1220 #[doc = "VIMS"]
1221 pub VIMS: VIMS,
1222 #[doc = "WDT"]
1223 pub WDT: WDT,
1224}
1225impl Peripherals {
1226 #[doc = r" Returns all the peripherals *once*"]
1227 #[inline]
1228 pub fn take() -> Option<Self> {
1229 cortex_m::interrupt::free(|_| {
1230 if unsafe { DEVICE_PERIPHERALS } {
1231 None
1232 } else {
1233 Some(unsafe { Peripherals::steal() })
1234 }
1235 })
1236 }
1237 #[doc = r" Unchecked version of `Peripherals::take`"]
1238 pub unsafe fn steal() -> Self {
1239 debug_assert!(!DEVICE_PERIPHERALS);
1240 DEVICE_PERIPHERALS = true;
1241 Peripherals {
1242 AUX_ADI4: AUX_ADI4 {
1243 _marker: PhantomData,
1244 },
1245 AON_BATMON: AON_BATMON {
1246 _marker: PhantomData,
1247 },
1248 AON_EVENT: AON_EVENT {
1249 _marker: PhantomData,
1250 },
1251 AON_IOC: AON_IOC {
1252 _marker: PhantomData,
1253 },
1254 AON_PMCTL: AON_PMCTL {
1255 _marker: PhantomData,
1256 },
1257 AON_RTC: AON_RTC {
1258 _marker: PhantomData,
1259 },
1260 AUX_AIODIO0: AUX_AIODIO0 {
1261 _marker: PhantomData,
1262 },
1263 AUX_AIODIO1: AUX_AIODIO1 {
1264 _marker: PhantomData,
1265 },
1266 AUX_AIODIO2: AUX_AIODIO2 {
1267 _marker: PhantomData,
1268 },
1269 AUX_AIODIO3: AUX_AIODIO3 {
1270 _marker: PhantomData,
1271 },
1272 AUX_ANAIF: AUX_ANAIF {
1273 _marker: PhantomData,
1274 },
1275 AUX_EVCTL: AUX_EVCTL {
1276 _marker: PhantomData,
1277 },
1278 AUX_MAC: AUX_MAC {
1279 _marker: PhantomData,
1280 },
1281 AUX_SCE: AUX_SCE {
1282 _marker: PhantomData,
1283 },
1284 AUX_SMPH: AUX_SMPH {
1285 _marker: PhantomData,
1286 },
1287 AUX_SPIM: AUX_SPIM {
1288 _marker: PhantomData,
1289 },
1290 AUX_SYSIF: AUX_SYSIF {
1291 _marker: PhantomData,
1292 },
1293 AUX_TDC: AUX_TDC {
1294 _marker: PhantomData,
1295 },
1296 AUX_TIMER01: AUX_TIMER01 {
1297 _marker: PhantomData,
1298 },
1299 AUX_TIMER2: AUX_TIMER2 {
1300 _marker: PhantomData,
1301 },
1302 CCFG: CCFG {
1303 _marker: PhantomData,
1304 },
1305 CPU_DWT: CPU_DWT {
1306 _marker: PhantomData,
1307 },
1308 CPU_FPB: CPU_FPB {
1309 _marker: PhantomData,
1310 },
1311 CPU_ITM: CPU_ITM {
1312 _marker: PhantomData,
1313 },
1314 CPU_SCS: CPU_SCS {
1315 _marker: PhantomData,
1316 },
1317 CPU_TIPROP: CPU_TIPROP {
1318 _marker: PhantomData,
1319 },
1320 CPU_TPIU: CPU_TPIU {
1321 _marker: PhantomData,
1322 },
1323 CRYPTO: CRYPTO {
1324 _marker: PhantomData,
1325 },
1326 AUX_DDI0_OSC: AUX_DDI0_OSC {
1327 _marker: PhantomData,
1328 },
1329 EVENT: EVENT {
1330 _marker: PhantomData,
1331 },
1332 FCFG1: FCFG1 {
1333 _marker: PhantomData,
1334 },
1335 FLASH: FLASH {
1336 _marker: PhantomData,
1337 },
1338 GPIO: GPIO {
1339 _marker: PhantomData,
1340 },
1341 GPT0: GPT0 {
1342 _marker: PhantomData,
1343 },
1344 GPT1: GPT1 {
1345 _marker: PhantomData,
1346 },
1347 GPT2: GPT2 {
1348 _marker: PhantomData,
1349 },
1350 GPT3: GPT3 {
1351 _marker: PhantomData,
1352 },
1353 I2C0: I2C0 {
1354 _marker: PhantomData,
1355 },
1356 I2S0: I2S0 {
1357 _marker: PhantomData,
1358 },
1359 IOC: IOC {
1360 _marker: PhantomData,
1361 },
1362 PKA: PKA {
1363 _marker: PhantomData,
1364 },
1365 PKA_INT: PKA_INT {
1366 _marker: PhantomData,
1367 },
1368 PRCM: PRCM {
1369 _marker: PhantomData,
1370 },
1371 RFC_DBELL: RFC_DBELL {
1372 _marker: PhantomData,
1373 },
1374 RFC_PWR: RFC_PWR {
1375 _marker: PhantomData,
1376 },
1377 RFC_RAT: RFC_RAT {
1378 _marker: PhantomData,
1379 },
1380 SMPH: SMPH {
1381 _marker: PhantomData,
1382 },
1383 SRAM_MMR: SRAM_MMR {
1384 _marker: PhantomData,
1385 },
1386 SSI0: SSI0 {
1387 _marker: PhantomData,
1388 },
1389 SSI1: SSI1 {
1390 _marker: PhantomData,
1391 },
1392 TRNG: TRNG {
1393 _marker: PhantomData,
1394 },
1395 UART0: UART0 {
1396 _marker: PhantomData,
1397 },
1398 UART1: UART1 {
1399 _marker: PhantomData,
1400 },
1401 UDMA0: UDMA0 {
1402 _marker: PhantomData,
1403 },
1404 VIMS: VIMS {
1405 _marker: PhantomData,
1406 },
1407 WDT: WDT {
1408 _marker: PhantomData,
1409 },
1410 }
1411 }
1412}